# US 9,520,628 B2 · Transistor switches with single-polarity control voltage > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,520,628 B2 - Document ID: US9520628B2 - Status: Granted - Kind: B2 - Application number: 14/527,501 - Filed: 2014-10-29 - Published: 2015-05-07 - Granted: 2016-12-13 - Earliest claimed: 2011-07-20 - Assignees: ViaSat, Inc. - Applicants: ViaSat, Inc. - Inventors: Christopher D. Grondahl; Donald E. Crockett, III - Web page: https://patentgrep.com/patent/US9520628B2 ## CPC - H01P 1/15: by semiconductor devices - H01P 1/18: Phase-shifters (H01P1/165 takes precedence) - H03H 11/20: Two-port phase shifters providing an adjustable phase shift - H03K 17/693: Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00) - H01P: WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE (operating at optical frequencies G02B) - H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Contrary to phase shifters which require complimentary polarity control voltages, a phase shifter may be driven with a single polarity control voltage. The phase shifter comprises an input node in communication with both a high pass network and a low pass network which are both in communication with an output node, where the phase shifter further comprises a first single pole double throw switch and a second single pole double throw switch configured to selectively pass an RF signal from the input node to the output node by way of one of said high pass network and said low pass network. Furthermore, the first and second single pole double throw switches are configured to select between the high pass network and the low pass network based on a single control signal having a voltage greater than or less than a reference voltage. ## Claims ### Claim 1 A single pole double throw (SPDT) field-effect transistor (FET) switch comprising: a first FET comprising a first gate terminal, a first drain terminal, and a first source terminal; a second FET comprising a second gate terminal, a second drain terminal, and a second source terminal; an RF input node to communicate an RF input signal to the first and second drain terminals; a first RF output node connected to the first source terminal; a second RF output node connected to the second source terminal; a first reference voltage node to bias the first source terminal and the first drain terminal based on a first reference signal, wherein a first bias circuit element is connected between the first source terminal and the first drain terminal, wherein the first reference voltage node is connected to the first source terminal, and wherein the first reference voltage node is connected to the first drain terminal via the first bias circuit element; a control voltage node to provide a single control signal to the first gate terminal, and to bias the second source terminal and the second drain terminal based on the single control signal, wherein a second bias circuit element is connected between the second source terminal and the second drain terminal, wherein the control voltage node is connected to the second source terminal, and wherein the control voltage node is connected to the second drain terminal via the second bias circuit element; and a second reference voltage node to provide a second reference signal to bias the second gate terminal. ### Claim 2 (depends on 1) The SPDT FET switch of claim 1, wherein the second reference voltage node is a DC ground. ### Claim 3 (depends on 1) The SPDT FET switch of claim 1, wherein the first bias circuit element comprises a first resistor, and wherein the second bias circuit element comprises a second resistor. ### Claim 4 (depends on 1) The SPDT FET switch of claim 1, further comprising: a first shunt FET located between the first RF output node and the first FET, wherein the first shunt FET is biased by the single control signal from the control voltage node, and the second reference voltage node provides the second reference signal to a gate of the first shunt FET; a second shunt FET located between the second RF output node and the second FET, wherein the second shunt FET is biased by the first reference signal from the first reference voltage node, and the control voltage node provides the single control signal to a gate of the second shunt FET. ### Claim 5 (depends on 1) The SPDT FET switch of claim 1, wherein the first FET turns on and the second FET turns off in response to a first voltage level of the single control signal, wherein the first FET turns off and the second FET turns on in response to a second voltage level of the single control signal, wherein the first voltage level is greater than the voltage level of the first reference signal, wherein the second voltage level is less than the voltage level of the first reference signal, and wherein the first voltage level is a positive voltage. ### Claim 6 (depends on 1) The SPDT FET switch of claim 1, wherein a first RF path is from the RF input node, through the first FET, to the first RF output node, wherein a second RF path is from the RF input node, through the second FET, to the second RF output node, and wherein the first RF path and the second RF path comprise identical passive elements. ### Claim 7 A single pole double throw (SPDT) field-effect transistor (FET) switch comprising: a first FET comprising a first drain terminal and a first source terminal; a second FET comprising a second drain terminal and a second source terminal; an RF input node to communicate an RF input signal to the first and second drain terminals; a first RF output node connected to the first source terminal; a second RF output node connected to the second source terminal; a first reference voltage node to bias the first FET based on a first reference signal from the first reference voltage node; a control voltage node to provide a control signal to the first FET and to bias the second FET based on the control signal; and a second reference voltage node to provide a second reference signal to the second FET; wherein the first FET turns on and the second FET turns off in response to a first voltage level of the control signal, wherein the first FET turns off and the second FET turns on in response to a second voltage level of the control signal, wherein the first voltage level is greater than a voltage level of the first reference signal, wherein the second voltage level is less than the voltage level of the first reference signal, and wherein the first voltage level is a positive voltage. ### Claim 8 (depends on 7) The SPDT FET switch of claim 7, wherein the SPDT FET switch is employed in a phase shifter. ### Claim 9 (depends on 7) The SPDT FET switch of claim 7, wherein the second voltage level is a negative voltage. ### Claim 10 (depends on 7) The SPDT FET switch of claim 7, wherein a first bias circuit element is connected between the first source terminal and the first drain terminal, wherein the first reference voltage node is connected to the first source terminal, and wherein the first reference voltage node is connected to the first drain terminal via the first bias circuit element; and wherein the control voltage node provides the control signal to a first gate terminal of the first FET, wherein a second bias circuit element is connected between the second source terminal and the second drain terminal, wherein the control voltage node is connected to the second source terminal, and wherein the control voltage node is connected to the second drain terminal via the second bias circuit element. ### Claim 11 (depends on 7) The SPDT FET switch of claim 7, further comprising: a first shunt FET located between the first RF output node and the first FET, wherein the first shunt FET is biased by the control signal from the control voltage node, and the second reference voltage node provides the second reference signal to a gate of the first shunt FET; and a second shunt FET located between the second RF output node and the second FET, wherein the second shunt FET is biased by the first reference signal from the first reference voltage node, and the control voltage node provides the control signal to a gate of the second shunt FET. ### Claim 12 (depends on 7) The SPDT FET switch of claim 7, wherein a first RF path is from the RF input node, through the first FET, to the first RF output node, wherein a second RF path is from the RF input node, through the second FET, to the second RF output node, and wherein the first RF path and the second RF path comprise identical passive elements. ### Claim 13 (depends on 7) The SPDT FET switch of claim 7, wherein the second reference voltage node is a DC ground. ### Claim 14 A single pole double throw (SPDT) field-effect transistor (FET) switch comprising: an RF input node; a first RF output node connected to the RF input node via a first FET, defining a first RF path; a second RF output node connected to the RF input node via a second FET, defining a second RF path; and a control voltage node to provide a single control signal that causes switching between the first RF path and the second RF path; wherein the first RF path and the second RF path are symmetric and comprise identical passive elements. ### Claim 15 (depends on 14) The SPDT FET switch of claim 14, further comprising: a first reference voltage node to bias a first drain terminal and a first source terminal of the first FET based on a first reference signal; a second reference voltage node to provide a second reference signal to a gate of the second FET; wherein the control voltage node biases a second drain terminal and a second source terminal of the second FET based on the single control signal from the control voltage node. ### Claim 16 (depends on 15) The SPDT FET switch of claim 15, wherein the control voltage node is connected to a gate of the first FET. ### Claim 17 (depends on 15) The SPDT FET switch of claim 15, further comprising: a first shunt FET located between the first RF output node and the first FET, wherein the first shunt FET is biased by the single control signal from the control voltage node, and the second reference voltage node provides the second reference signal to a gate of the first shunt FET; a second shunt FET located between the second RF output node and the second FET, wherein the second shunt FET is biased by the first reference signal from the first reference voltage node, and the control voltage node provides the single control signal to a gate of the second shunt FET. ### Claim 18 (depends on 15) The SPDT FET switch of claim 15, wherein a first bias circuit element is connected between the first source terminal and the first drain terminal of the first FET, wherein the first reference voltage node is connected to the first source terminal, and wherein the first reference voltage node is connected to the first drain terminal via the first bias circuit element; and wherein the control voltage node provides the single control signal to a gate of the first FET, wherein a second bias circuit element is connected between the second source terminal and the second drain terminal, wherein the control voltage node is connected to the second source terminal, and wherein the control voltage node is connected to the second drain terminal via the second bias circuit element. ### Claim 19 (depends on 15) The SPDT FET switch of claim 15, wherein the second reference voltage node is DC ground. ### Claim 20 (depends on 15) The SPDT FET switch of claim 15, wherein the first FET turns on and the second FET turns off in response to a first voltage level of the single control signal, wherein the first FET turns off and the second FET turns on in response to a second voltage level of the single control signal, wherein the first voltage level is greater than the voltage level of the first reference signal, wherein the second voltage level is less than the voltage level of the first reference signal, and wherein the first voltage level is a positive voltage.