# US 9,520,561 B1 · Controlling on-state current for two-terminal memory

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- Number: US 9,520,561 B1
- Document ID: US9520561B1
- Status: Granted
- Kind: B1
- Application number: 14/798,074
- Filed: 2015-07-13
- Granted: 2016-12-13
- Earliest claimed: 2013-03-14
- Assignees: Crossbar, Inc.
- Applicants: Crossbar, Inc.
- Inventors: Kuk-Hwan Kim; Ping Lu; Chen-Chun Chen; Sung Hyun Jo
- Web page: https://patentgrep.com/patent/US9520561B1

## CPC

- H10N 70/021: {Formation of switching materials, e.g. deposition of layers}
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/24: {based on migration or redistribution of ionic species, e.g. anions, vacancies}
- H10N 70/245: {the species being metal cations, e.g. programmable metallization cells}
- H10N 70/801: {Constructional details of multistable switching devices}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/883: {Oxides or nitrides}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10N 70/884: {based on at least one element of group IIIA, IVA or VA, e.g. elemental or compound semiconductors (compounds of sulfur, selenium or tellurium, e.g. chalcogenides H10N70/882; oxides or nitrides H10N70/883)}
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

Provision of fabrication, construction, and/or assembly of a memory device including a two-terminal memory portion is described herein. The two-terminal memory device fabrication can provide enhanced capabilities in connection with precisely tuning on-state current over a greater possible range.

## Claims

### Claim 1

A method for fabricating a memory device, comprising:
forming a two-terminal memory layer above a substrate layer;
including in the two-terminal memory layer an ohmic contact layer above the substrate layer, a resistive layer above the ohmic contact layer, a resistive switching material (RSM) layer above the resistive layer, and an active metal layer above the RSM layer;
including a first semiconductor material layer in an amorphous phase in the resistive layer; and
including a second semiconductor material layer in a polycrystalline phase in the resistive layer situated above the first semiconductor layer.

### Claim 2 (depends on 1)

The method of claim 1, further comprising forming the second semiconductor material layer from a p-type conductive semiconductor material comprising polycrystalline silicon germanium (SiGe).

### Claim 3 (depends on 1)

The method of claim 1, further comprising forming the second semiconductor material with a resistivity in a range of about 0.001 ohm-centimeters to about 0.5 ohm-centimeters.

### Claim 4 (depends on 3)

The method of claim 3, further comprising forming the second semiconductor material with a thickness in a range of about 5 nanometers to about 50 nanometers.

### Claim 5 (depends on 1)

The method of claim 1, further comprising receiving a resistance data associated with a target resistance for the resistive layer.

### Claim 6 (depends on 5)

The method of claim 5, further comprising determining from the resistance data a thickness value for the resistive layer associated with the target resistance.

### Claim 7 (depends on 6)

The method of claim 6, further comprising forming the second semiconductor material layer with a thickness equal to the thickness value.

### Claim 8 (depends on 1)

The method of claim 1, further comprising forming the RSM layer from an undoped amorphous silicon material or a silicon sub-oxide material.

### Claim 9 (depends on 1)

The method of claim 1, further comprising forming the RSM layer from a titanium oxide material.

### Claim 10 (depends on 1)

The method of claim 1, further comprising forming the RSM layer from a silicon oxide layer.

### Claim 11 (depends on 1)

The method of claim 1, further comprising forming the RSM layer from a first sub-layer comprising a titanium oxide material, and from a second sub-layer adjacent to the first sub-layer comprising a silicon sub-oxide material.

### Claim 12 (depends on 1)

The method of claim 1, further comprising forming a barrier layer adjacent to the RSM layer and the active metal layer, wherein the barrier layer comprises at least one of titanium, titanium oxide, tungsten, or titanium nitride.

### Claim 13 (depends on 1)

The method of claim 1, further comprising: forming the first semiconductor material and the second semiconductor material at a temperature that is within a thermal budget of a complementary metal oxide semiconductor device formed at least in part within the substrate layer.

### Claim 14 (depends on 13)

The method of claim 13, further comprising forming the first semiconductor material and the second semiconductor material at a temperature equal to or below about 450° C.

### Claim 15 (depends on 1)

The method of claim 1, further comprising forming the second semiconductor material in physical contact with the RSM layer.

### Claim 16

A method of fabricating a non-volatile memory, comprising:
providing a substrate having a complementary metal oxide semiconductor (CMOS) device within the substrate;
forming a dielectric layer over the substrate;
forming a first metal layer over the dielectric layer;
forming a resistive layer over the first metal layer, wherein forming the resistive layer further comprises forming an amorphous phase material overlying the first metal layer and forming a polycrystalline phase material overlying the amorphous phase material;
forming a resistive switching material (RSM) layer over the resistive layer; and
forming an active metal layer over the RSM layer.

### Claim 17 (depends on 16)

The method of claim 16, further comprising forming the non-volatile memory within a thermal budget of the CMOS device.

### Claim 18 (depends on 16)

The method of claim 16, further comprising forming the RSM layer adjacent to the crystalline phase material.

### Claim 19 (depends on 16)

The method of claim 16, wherein forming the resistive layer further comprises forming the amorphous phase material and the polycrystalline phase material, respectively, as a p-type semiconductor material.

### Claim 20 (depends on 16)

The method of claim 16, further comprising at least one of:
forming the amorphous phase material with a resistivity within a range between about 5 ohm-centimeters and about 50 ohm-centimeters; or
forming the polycrystalline phase material with a second resistivity within a second range between about 0.001 ohm-centimeters and about 0.5 ohm-centimeters.