# US 9,520,559 B2 · Heterojunction oxide non-volatile memory device

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- Number: US 9,520,559 B2
- Document ID: US9520559B2
- Status: Granted
- Kind: B2
- Application number: 14/874,152
- Filed: 2015-10-02
- Published: 2016-04-28
- Granted: 2016-12-13
- Earliest claimed: 2009-08-14
- Assignees: 4D-S Pty, Ltd
- Applicants: 4D-S, Pty, Ltd
- Inventors: Dongmin Chen
- Web page: https://patentgrep.com/patent/US9520559B2

## CPC

- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- G11C 11/5685: {using storage elements comprising metal oxide memory material, e.g. perovskites}
- G11C 13/0002: {using resistive RAM [RRAM] elements}
- G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites}
- G11C 13/0023: {Address circuits or decoders}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 13/0097: {Erasing, e.g. resetting, circuits or methods}
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10N 70/021: {Formation of switching materials, e.g. deposition of layers}
- H10N 70/026: {by physical vapor deposition, e.g. sputtering}
- H10N 70/028: {by conversion of electrode material, e.g. oxidation}
- H10N 70/24: {based on migration or redistribution of ionic species, e.g. anions, vacancies}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10N 70/8836: {Complex metal oxides, e.g. perovskites, spinels}
- G11C 2213/31: Material having complex metal oxide, e.g. perovskite structure
- G11C 2213/32: Material having simple binary metal oxide structure
- G11C 2213/77: Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A memory device includes a first metal layer and a first metal oxide layer coupled to the first metal layer. The memory device includes a second metal oxide layer coupled to the first metal oxide layer and a second metal layer coupled to the second metal oxide layer. The formation of the first metal oxide layer has a Gibbs free energy that is lower than the Gibbs free energy for the formation of the second metal oxide layer.

## Claims

### Claim 1

A method, comprising:
providing a plurality of switching devices, the switching devices arranged in an array of bitlines and wordlines, wherein each switching device comprises a first memory device which yields a clock wise current to a voltage hysteresis loop and a second memory device coupled to the first memory device, wherein the second memory device, yields a counter clock wise current to the voltage hysteresis loop; and
addressing a selected switching device within the array of bitlines and wordlines, wherein the selected switching device is located within a selected bitline and a selected wordline, wherein the addressing comprises:
applying a selected wordline voltage;
applying a selected bitline voltage;
applying an unselected wordline voltage to wordlines not selected; and
applying an unselected bitline voltage to bitlines not selected.

### Claim 2 (depends on 1)

The method of claim 1, wherein:
the addressing of the selected switching device is part of a programming operation;
the selected bitline voltage is a programming voltage;
the unselected bitline voltage is about one-third of the programming voltage;
the unselected wordline voltage is about two-thirds of the programming voltage; and
the selected wordline voltage is about zero.

### Claim 3 (depends on 1)

The method of claim 1, wherein:
the addressing of the selected switching device is part of an erasing operation;
the selected wordline voltage is an erase voltage;
the unselected wordline voltage is about one-third of the erase voltage;
the unselected bitline voltage is about two-thirds of the erase voltage; and
the selected bitline voltage is about zero.

### Claim 4 (depends on 1)

The method of claim 1, wherein the first memory device comprises:
a first metal layer;
a first metal oxide layer coupled to the first metal layer;
a second metal oxide layer coupled to the first metal oxide layer; and
a second metal layer coupled to the second metal oxide layer.

### Claim 5 (depends on 4)

The method of claim 4, wherein a Gibbs free energy for the formation of the first metal oxide layer is lower than the Gibbs free energy for the formation of the second metal oxide layer.

### Claim 6 (depends on 5)

The method of claim 5, wherein a metal in the first metal oxide layer is different from a metal in the first metal layer.

### Claim 7 (depends on 4)

The method of claim 4, wherein the first metal oxide comprises one of: TiO2, Ta2O5, NiO, WO3, or Al2O3, and the second metal oxide layer comprises Praseodymium Calcium Manganese Oxide (PCMO).

### Claim 8 (depends on 4)

The method of claim 4, wherein the first metal oxide comprises a first switchable resistance and the second metal oxide comprises a second switchable resistance.

### Claim 9 (depends on 4)

The method of claim 4, wherein the first metal oxide layer is characterized by a first high resistance and a first low resistance and the second metal oxide layer is characterized by a second high resistance and a second low resistance and wherein the first high resistance of the first metal oxide layer is greater than the second high resistance of the second metal oxide layer and the first low resistance of the first metal oxide is substantially similar to the second high resistance of the second metal oxide layer.

### Claim 10 (depends on 1)

The method of claim 1, wherein the first memory device is characterized by a first state having a first resistance and a second state having a second resistance and the second memory device is characterized by a third state having a third resistance state and a fourth state having a fourth resistance, and wherein the first resistance is higher than the second resistance and the third resistance is higher than the fourth resistance.

### Claim 11 (depends on 10)

The method of claim 10, wherein it can be identified whether the first memory device is in the first or the second state by performing a non-destructive read.

### Claim 12 (depends on 10)

The method of claim 10, wherein it can be identified whether the second memory device is in the third or the fourth state by performing a non-destructive read.

### Claim 13 (depends on 10)

The method of claim 10, wherein the first resistance is substantially different from the third resistance.

### Claim 14 (depends on 10)

The method of claim 10, wherein the second resistance is substantially different from the forth resistance.

### Claim 15 (depends on 4)

The method of claim 4, wherein the clockwise voltage hysteresis loop of the first memory device and the counter-clockwise voltage hysteresis loop of the second memory device are asymmetric in magnitude.