# US 9,520,557 B2 · Silicon based nanoscale crossbar memory

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- Number: US 9,520,557 B2
- Document ID: US9520557B2
- Status: Granted
- Kind: B2
- Application number: 14/857,508
- Filed: 2015-09-17
- Published: 2016-01-07
- Granted: 2016-12-13
- Earliest claimed: 2008-10-20
- Assignees: The Regents of the University of Michigan
- Applicants: The Regents of the University of Michigan
- Inventors: Wei Lu; Sung Hyun Jo; Kuk-Hwan Kim
- Web page: https://patentgrep.com/patent/US9520557B2

## CPC

- H10N 70/841: {Electrodes}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- G11C 11/5614: {using conductive bridging RAM [CBRAM] or programming metallization cells [PMC]}
- G11C 13/0011: {comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 13/0097: {Erasing, e.g. resetting, circuits or methods}
- H10B 63/20: {comprising selection components having two electrodes, e.g. diodes}
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10B 63/82: {the switching components having a common active material layer}
- H10N 70/021: {Formation of switching materials, e.g. deposition of layers}
- H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography}
- H10N 70/245: {the species being metal cations, e.g. programmable metallization cells}
- H10N 70/821: {Device geometry}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/8416: {adapted for supplying ionic species}
- H10N 70/884: {based on at least one element of group IIIA, IVA or VA, e.g. elemental or compound semiconductors (compounds of sulfur, selenium or tellurium, e.g. chalcogenides H10N70/882; oxides or nitrides H10N70/883)}
- B82Y 30/00: Nanotechnology for materials or surface science, e.g. nanocomposites
- G11C 2013/005: {Read using potential difference applied between cell electrodes}
- G11C 2013/0071: {Write using write potential applied to access device gate}
- G11C 2213/11: Metal ion trapping, i.e. using memory material including cavities, pores or spaces in form of tunnels or channels wherein metal ions can be trapped but do not react and form an electro-deposit creating filaments or dendrites
- G11C 2213/33: Material including silicon
- G11C 2213/77: Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
- G11C 2213/81: Array wherein the array conductors, e.g. word lines, bit lines, are made of nanowires
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

The present application describes a crossbar memory array. The memory array includes a first array of parallel nanowires of a first material and a second array of parallel nanowires of a second material. The first and the second array are oriented at an angle with each other. The array further includes a plurality of nanostructures of non-crystalline silicon disposed between a nanowire of the first material and a nanowire of the second material at each intersection of the two arrays. The nanostructures form a resistive memory cell together with the nanowires of the first and second materials.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor substrate;
a first array of electrodes disposed above the semiconductor substrate, wherein the first array of electrodes comprise a first metal-containing material, wherein the first metal is selected from a group consisting of: aluminum, nickel, platinum and tungsten;
a second array of electrodes disposed above the first array of electrodes, wherein the second array of electrodes are oriented at an angle with respect to the first array of electrodes, wherein the first array of electrodes and the second array of electrodes overlap at a plurality of intersections, wherein the second array of electrodes comprises a second metal-containing material; and
a plurality of resistive switching nanostructures disposed between the first array of electrodes and the second array of electrodes, wherein each resistive switching nanostructure provides a contact point between the first array of electrodes and the second array of electrodes at exactly one intersection from the plurality of intersections, wherein the plurality of resistive switching nanostructures comprises an undoped silicon-containing material having a number of defect sites; and
wherein particles of the first metal derived from the first metal-containing material are diffused within defect sites of at least one resistive switching nanostructure from the plurality of resistive switching nanostructures, and wherein the particles of the first metal form a conductive filament within the one resistive switching nanostructure.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the undoped silicon-containing material is selected from a group consisting of: amorphous silicon and non-crystalline silicon.

### Claim 3 (depends on 1)

The semiconductor device memory array of claim 1, wherein the second metal is selected from a group consisting of: nickel (Ni) and platinum (Pt).

### Claim 4 (depends on 1)

The semiconductor device of claim 1,
wherein the substrate comprises a plurality of circuits; and
wherein the first array of electrodes and the second array of electrodes are coupled to at least one circuit of the plurality of circuits.

### Claim 5 (depends on 4)

The semiconductor device of claim 4 wherein the circuit is selected from a group consisting of: a decoding circuit, a writing circuit, an erasing circuit and a reading circuit.

### Claim 6 (depends on 4)

The semiconductor device of claim 4 wherein the circuit comprises a multi-level programming circuit.

### Claim 7 (depends on 6)

The semiconductor device of claim 6 wherein the multi-level programming circuit comprises a plurality of resistances.

### Claim 8

A method for fabricating a semiconductor device comprising:
receiving a semiconductor substrate;
forming a first array of electrodes above the semiconductor substrate, wherein the first array of electrodes comprises a first metal-containing material;
forming a plurality of resistive switching nanostructures above the first array of electrodes, wherein the plurality of resistive switching nanostructures comprises an undoped silicon-containing material having a number of defect sites; and
forming a second array of electrodes above the plurality of resistive switching nanostructures, wherein the second array of electrodes are oriented at an angle with respect to the first array of electrodes, wherein the first array of electrodes and the second array of electrodes overlap at a plurality of intersections, wherein each resistive switching nanostructure from the plurality of resistive switching nanostructures provides a contact point between the first array of electrodes and the second array of electrodes at exactly one intersection from the plurality of intersections, wherein the second array of electrodes comprise a second metal-containing material, and wherein the second metal is selected from a group consisting of: aluminum, nickel, platinum and tungsten;
wherein particles of the second metal from the second metal-containing material are configured to diffuse within defect sites of at least one resistive switching nanostructure from the plurality of resistive switching nanostructures to thereby form a conductive filament within the one resistive switching nanostructure.

### Claim 9 (depends on 8)

The method of claim 8 wherein the forming the plurality of resistive switching nanostructures comprises depositing a material selected from a group consisting of: amorphous silicon and non-crystalline silicon.

### Claim 10 (depends on 8)

The method of claim 8 wherein the forming the first array comprises depositing a material selected from a group consisting of: nickel (Ni)-containing material and platinum (Pt) containing material.

### Claim 11 (depends on 8)

The method of claim 8
wherein receiving the semiconductor substrate comprises forming a plurality of circuits within the semiconductor substrate; and
coupling the first array of electrodes and the second array of electrodes to at least one circuit of the plurality of circuits.

### Claim 12 (depends on 11)

The method of claim 11 wherein the forming the plurality of circuits comprises forming a circuit selected from a group consisting of” a decoding circuit, a writing circuit, an erasing circuit and a reading circuit.

### Claim 13 (depends on 11)

The method of claim 11 wherein the forming the plurality of circuits comprises forming a multi-level programming circuit.

### Claim 14 (depends on 13)

The method of claim 13 wherein the forming the multi-level programming circuit comprises forming a plurality of resistors.

### Claim 15

A method for operating a semiconductor device comprising a semiconductor substrate comprises:
applying a first voltage across a first electrode from a first array of electrodes and a first electrode from a second array of electrodes through a resistive switching nanostructure of a plurality of resistive switching nanostructures, to thereby induce a first current flow between the first electrode from the second array of electrodes and the first electrode from the first array of electrodes, wherein the first array of electrodes are disposed above the semiconductor substrate, wherein the first array of electrodes comprises a first metal-containing material, a plurality of resistive switching nanostructures above the first array of electrodes, wherein the plurality of resistive switching nanostructures comprises an undoped silicon-containing material having a number of defect sites, and wherein the second array of electrodes are disposed above the plurality of resistive switching nanostructures, wherein the second array of electrodes are oriented at an angle with respect to the first array of electrodes, wherein the first array of electrodes and the second array of electrodes overlap at a plurality of intersections, wherein each resistive switching nanostructure from the plurality of resistive switching nanostructures provides a contact point between the first array of electrodes and the second array of electrodes at exactly one intersection from the plurality of intersections, wherein the second array of electrodes comprise a second metal-containing material, and wherein the second metal is selected from a group consisting of: aluminum, nickel, platinum and tungsten; and
determining a first resistance state of the resistive switching nanostructure in response to the first current flow.

### Claim 16 (depends on 15)

The method of claim 15 further comprising:
applying a second voltage across the first electrode from the second array of electrodes and the first electrode from the first array of electrodes, to thereby diffuse particles of the second metal from the first metal-containing material into defect sites of the resistive switching nanostructure, and to thereby form a conductive filament within the one resistive switching nanostructure; and
terminating applying the second voltage, wherein the conductive filament remains formed within the one resistive switching nanostructure.

### Claim 17 (depends on 16)

The method of claim 16 wherein after terminating applying the second voltage, the method further comprises:
applying the first voltage across the first electrode from the second array of electrodes and the first electrode from the first array of electrodes through the resistive switching nanostructure to thereby induce a second current flow between the first electrode from the second array of electrodes and the first electrode from the first array of electrodes; and
determining a second resistance state of the resistive switching nanostructure in response to the second current flow.

### Claim 18 (depends on 17)

The method of claim 17 wherein the second current flow is larger than the first current flow.

### Claim 19 (depends on 16)

The method of claim 16 wherein after terminating applying the second voltage, the method further comprises:
applying the third voltage across the first electrode from the array of electrodes and the first electrode from the second array of electrodes through the resistive switching nanostructure to thereby withdraw at least some particles of the first metal from defect sites of the resistive switching nanostructure to the first electrode from the second array of electrodes, and to thereby reduce the conductive filament within the one resistive switching nanostructure.

### Claim 20 (depends on 19)

The method of claim 19 wherein the second voltage has a polarity opposite of a polarity of the third voltage.