# US 9,520,547 B2 · Chip mode isolation and cross-talk reduction through buried metal layers and through-vias

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- Number: US 9,520,547 B2
- Document ID: US9520547B2
- Status: Granted
- Kind: B2
- Application number: 13/838,261
- Filed: 2013-03-15
- Published: 2014-09-18
- Granted: 2016-12-13
- Earliest claimed: 2013-03-15
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: David W. Abraham; George A. Keefe; Christian Lavoie; Mary E. Rothwell
- Web page: https://patentgrep.com/patent/US9520547B2

## CPC

- H10N 60/815: {for Josephson-effect devices}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10N 60/0912: {of Josephson-effect devices}
- H10N 60/12: Josephson-effect devices
- H10W 20/021: {of interconnections within wafers or substrates}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/4484: {Superconducting materials}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- H10N 69/00: Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A method for fabricating a chip surface base includes preparing a first substrate, preparing a plurality of vias in the first substrate, depositing metal fillings into the plurality of vias, preparing a second substrate, bonding the first and second substrates and exposing the metal fillings. A method for fabricating a chip surface base includes preparing a first and second substrate, depositing a metal on at least one of the first and second substrates, bonding the first and second substrates, preparing a plurality of vias in the first substrate, depositing metal fillings into the plurality of vias and exposing the metal fillings. A chip surface base device includes a first substrate, a second substrate, a metal layer disposed between the first and second substrates and a plurality vias disposed on the first substrate.

## Claims

### Claim 1

A method for fabricating a chip surface base, the method comprising:
preparing a first substrate;
forming a plurality of vias in a top surface of the first substrate;
depositing metal fillings into the plurality of vias;
forming a first metal layer on the top surface of the first substrate and in contact with the plurality of vias;
preparing a second substrate;
forming a second metal layer on a top surface of the second substrate;
bonding the first and second substrates at the first and second metal layers so as to form a bonded, buried metal layer;
polishing a bottom surface of the first substrate so as to expose the metal fillings, wherein the resultant structure comprises the first substrate contacting the first metal layer, the second substrate contacting the second metal layer and the first metal layer contacting the second metal layer; and
etching the first and second substrates to fabricate a qubit circuit;
fabricating a qubit circuit, wherein the qubit circuit is on the first substrate and is coupled to a plurality of chip modes, the plurality of chip modes operative to conduct into the metal fillings deposited into the plurality of vias and define a short into the metal layer between the second substrate and the first substrate, wherein the plurality of chip modes have wavelengths longer than distances between vias in the plurality of vias; and
wherein the plurality of vias is arranged in a location on the first substrate such that the plurality of vias isolates the plurality of chip modes between the plurality of vias and the metal layer between the second substrate and the first substrate.

### Claim 2 (depends on 1)

The method as claimed in claim 1, further comprising:
selecting the first and second substrates to reduce dielectric loss tangent at superconducting temperatures.

### Claim 3 (depends on 1)

The method as claimed in claim 1, wherein the plurality of vias is etched into the top surface of the first substrate.

### Claim 4 (depends on 3)

The method as claimed in claim 3, further comprising: selecting locations of vias on the top surface of the first substrate to correspond to mode locations of the fabricated qubit circuit.

### Claim 5 (depends on 1)

The method as claimed in claim 1, wherein the first and second metal layers are a same material as the metal fillings.

### Claim 6 (depends on 5)

The method as claimed in claim 5, wherein the first and second metal layers and the metal fillings are a superconducting material.