# US 9,520,503 B2 · Semiconductor device and method for manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,520,503 B2 - Document ID: US9520503B2 - Status: Granted - Kind: B2 - Application number: 15/049,566 - Filed: 2016-02-22 - Published: 2016-06-16 - Granted: 2016-12-13 - Earliest claimed: 2010-12-28 - Assignees: Semiconductor Energy Laboratory Co., Ltd. - Applicants: Semiconductor Energy Laboratory Co., Ltd. - Inventors: Shunpei Yamazaki - Web page: https://patentgrep.com/patent/US9520503B2 ## CPC - H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate} - H10D 30/6715: {characterised by the doping profiles, e.g. having lightly-doped source or drain extensions} - H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes} - H10D 30/6739: {Conductor-insulator-semiconductor electrodes} - H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)} - H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)} - H10D 62/40: Crystalline structures - H10D 62/60: Impurity distributions or concentrations - H10D 64/514: {characterised by the insulating layers} - H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)} - H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO} - H10D 86/425: {having different crystal properties in different TFTs or within an individual TFT} - H10D 86/60: wherein the TFTs are in active matrices - H10D 99/00: Subject matter not provided for in other groups of this subclass - H10P 14/22: using physical deposition, e.g. vacuum deposition or sputtering - H10P 14/3426: {Oxides} - H10P 14/3434: {being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424)} - H10P 30/22: using masks - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device in which fluctuation in electric characteristics due to miniaturization is less likely to be caused is provided. The semiconductor device includes an oxide semiconductor film including a first region, a pair of second regions in contact with side surfaces of the first region, and a pair of third regions in contact with side surfaces of the pair of second regions; a gate insulating film provided over the oxide semiconductor film; and a first electrode that is over the gate insulating film and overlaps with the first region. The first region is a CAAC oxide semiconductor region. The pair of second regions and the pair of third regions are each an amorphous oxide semiconductor region containing a dopant. The dopant concentration of the pair of third regions is higher than the dopant concentration of the pair of second regions. ## Claims ### Claim 1 A semiconductor device comprising: a gate electrode; a gate insulating film over the gate electrode; an oxide semiconductor film over the gate insulating film, the oxide semiconductor film comprising: a first region; a pair of second regions, the first region located between the pair of second regions; and a pair of third regions, the first region and the pair of second regions located between the pair of third regions; and an insulating film overlapped with the first region, wherein the pair of second regions is overlapped with the gate electrode, wherein a crystallinity of the first region and a crystallinity of the pair of third regions are higher than a crystallinity of the pair of second regions. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein an energy level of a bottom of a conductive band of the first region is higher than an energy level of a bottom of a conductive band of the pair of second regions. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the first region is a c-axis aligned crystal oxide semiconductor region. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, further comprising: a source electrode electrically connected to one of the pair of third regions; and a drain electrode electrically connected to the other of the pair of third regions. ### Claim 5 (depends on 4) The semiconductor device according to claim 4, wherein the source electrode is in contact with a top surface of the one of the pair of third regions, and wherein the drain electrode is in contact with a top surface of the other of the pair of third regions. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein the gate insulating film overlaps with the first region, the pair of second regions, and the pair of third regions. ### Claim 7 (depends on 1) The semiconductor device according to claim 1, wherein the gate insulating film is an oxide insulating film. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, wherein the pair of second regions comprises one or more elements selected from nitrogen, phosphorus, and arsenic, and wherein a dopant concentration of the pair of second regions is higher than or equal to 5×1018 atoms/cm3 and lower than or equal to 1×1022 atoms/cm3. ### Claim 9 (depends on 1) The semiconductor device according to claim 1, wherein the pair of second regions comprises one or more elements selected from nitrogen, phosphorus, and arsenic, wherein a dopant concentration of the pair of second regions is higher than or equal to 5×1018 atoms/cm3 and lower than 5×1019 atoms/cm3. ### Claim 10 (depends on 1) The semiconductor device according to claim 1, wherein the oxide semiconductor film comprises two or more elements selected from In, Ga, Sn, and Zn. ### Claim 11 A semiconductor device comprising: a gate electrode; a gate insulating film over the gate electrode; an oxide semiconductor film over the gate insulating film, the oxide semiconductor film comprising: a first region; a pair of second regions, the first region located between the pair of second regions; a pair of third regions, the first region and the pair of second regions located between the pair of third regions; and a pair of fourth regions, the first region, the pair of second regions and the pair of third regions located between the pair of fourth regions a source electrode electrically connected to one of the pair of fourth regions; a drain electrode electrically connected to the other of the pair of fourth regions; and, an insulating film overlapped with the first region, wherein the pair of second regions is overlapped with the gate electrode, wherein an end portion of the source electrode and an end portion of the drain electrode are tapered-shapes, wherein the end portion of the source electrode is overlapped with one of the pair of third regions, wherein the end portion of the drain electrode is overlapped with the other of the pair of third regions, wherein each of a crystallinity of the pair of second regions and a crystallinity of the pair of third regions is lower than a crystallinity of the first region, and wherein a dopant concentration of the pair of second regions is different from a dopant concentration of the pair of third regions. ### Claim 12 (depends on 11) The semiconductor device according to claim 11, wherein an energy level of a bottom of a conductive band of the first region is higher than an energy level of a bottom of a conductive band of the pair of second regions. ### Claim 13 (depends on 11) The semiconductor device according to claim 11, wherein the first region is a c-axis aligned crystal oxide semiconductor region. ### Claim 14 (depends on 11) The semiconductor device according to claim 11, wherein the source electrode is in contact with a top surface of the one of the pair of fourth regions, and wherein the drain electrode is in contact with a top surface of the other of the pair of fourth regions. ### Claim 15 (depends on 11) The semiconductor device according to claim 11, wherein the gate insulating film overlaps with the first region, the pair of second regions, the pair of third regions, and the pair of fourth regions. ### Claim 16 (depends on 11) The semiconductor device according to claim 11, wherein the gate insulating film is an oxide insulating film. ### Claim 17 (depends on 11) The semiconductor device according to claim 11, wherein the pair of second regions comprises one or more elements selected from nitrogen, phosphorus, and arsenic, and wherein the dopant concentration of the pair of second regions is higher than or equal to 5×1018 atoms/cm3 and lower than or equal to 1×1022 atoms/cm3. ### Claim 18 (depends on 11) The semiconductor device according to claim 11, wherein the pair of second regions comprises one or more elements selected from nitrogen, phosphorus, and arsenic, wherein the dopant concentration of the pair of second regions is higher than or equal to 5×1018 atoms/cm3 and lower than 5×1019 atoms/cm3. ### Claim 19 (depends on 11) The semiconductor device according to claim 11, wherein the oxide semiconductor film comprises two or more elements selected from In, Ga, Sn, and Zn.