# US 9,520,502 B2 · FinFETs having epitaxial capping layer on fin and methods for forming the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 9,520,502 B2
- Document ID: US9520502B2
- Status: Granted
- Kind: B2
- Application number: 14/054,595
- Filed: 2013-10-15
- Published: 2015-04-16
- Granted: 2016-12-13
- Earliest claimed: 2013-10-15
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Ming-Hua Yu; Chih-Pin Tsao; Hou-Yu Chen
- Web page: https://patentgrep.com/patent/US9520502B2

## CPC

- H10D 30/0241: {doping of vertical sidewalls, e.g. using tilted or multi-angled implants}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/611: {having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733)}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6212: {having fin-shaped semiconductor bodies having non-rectangular cross-sections}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D 62/53: the imperfections being within the semiconductor body
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10P 14/20: of semiconductor materials
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10P 50/242: {of Group IV materials}
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A FinFET and methods for forming a FinFET are disclosed. A method includes forming a semiconductor fin on a substrate, implanting the semiconductor fin with dopants, and forming a capping layer on a top surface and sidewalls of the semiconductor fin. The method further includes forming a dielectric on the capping layer, and forming a gate electrode on the dielectric.

## Claims

### Claim 1

A method comprising:
forming a semiconductor fin on a doped substrate, the semiconductor fin having a first region, a second region, and a third region, the second region being interposed between the first region and the third region;
forming an isolation region on the doped substrate, the isolation region surrounding the semiconductor fin;
implanting the semiconductor fin with dopants, the implanting the semiconductor fin with dopants causes twin plane defects in the semiconductor fin;
after implanting the semiconductor fin with dopants, recessing the isolation region to expose at least a portion of the semiconductor fin;
epitaxially growing a capping layer on a top surface and sidewalls of the exposed portion of the semiconductor fin in at least the second region of the semiconductor fin, the capping layer being formed over the twin plane defects;
after epitaxially growing the capping layer, forming a gate dielectric on the capping layer in the second region of the semiconductor fin; and
forming a gate electrode on the gate dielectric.

### Claim 2 (depends on 1)

The method of claim 1, wherein the capping layer is a homoepitaxial or heteroepitaxial structure.

### Claim 3 (depends on 1)

The method of claim 1, wherein the capping layer has a thickness from 2 nm to 6 nm.

### Claim 4 (depends on 1)

The method of claim 1, wherein the dopants comprise boron, phosphorous, arsenic, germanium, carbon, fluorine, indium, or a combination thereof.

### Claim 5 (depends on 1)

The method of claim 1 wherein the forming a semiconductor fin on a substrate further comprises:
patterning the substrate to form a semiconductor fin extending above the substrate.

### Claim 6 (depends on 1)

The method of claim 1 further comprising:
forming a source region in the first region of the semiconductor fin; and
forming a drain region in the third region of the semiconductor fin, the capping layer extending across the top surface of the second region of the semiconductor fin from the first region to the third region.

### Claim 7

A method comprising:
doping a substrate with dopants;
forming a semiconductor fin on the doped substrate;
forming an isolation region on the doped substrate, the isolation region surrounding the semiconductor fin;
implanting dopants into the semiconductor fin, the implanting dopants into the semiconductor fin causing twin plane defects in the semiconductor fin;
after implanting dopants into the semiconductor fin, recessing the isolation region to expose an upper portion of the semiconductor fin; and
epitaxially growing a capping layer on a top surface and sidewalls of the semiconductor fin, the top surface and sidewalls being on the upper portion of the semiconductor fin, the capping layer being a homoepitaxial structure, the capping layer being epitaxially grown over the twin plane defects.

### Claim 8 (depends on 7)

The method of claim 7, wherein a bottom surface of the capping layer adjoins a top surface of the isolation region.

### Claim 9 (depends on 7)

The method of claim 7 further comprising doping the capping layer as the capping layer is being grown.

### Claim 10 (depends on 7)

The method of claim 7 further comprising:
forming a gate dielectric on the capping layer; and
forming a gate electrode on the gate dielectric.

### Claim 11 (depends on 7)

The method of claim 7 further comprising:
after implanting dopants into the semiconductor fin and before recessing the isolation region, performing an anneal process on the semiconductor fin.

### Claim 12 (depends on 7)

The method of claim 7 further comprising:
before epitaxially growing the capping layer on the upper portion of the semiconductor fin, performing a dry etch process on the upper portion of the semiconductor fin.

### Claim 13 (depends on 7)

The method of claim 7, wherein the capping layer has a thickness from 2 nm to 6 nm.

### Claim 14 (depends on 7)

The method of claim 7, wherein the dopants comprise boron, phosphorous, arsenic, germanium, carbon, fluorine, indium, or a combination thereof.

### Claim 15 (depends on 7)

The method of claim 7 further comprising:
forming a second semiconductor fin on the doped substrate, before implanting dopants into the semiconductor fin, the isolation region surrounding the second semiconductor fin, the isolation region contacting opposite sidewalls of both the semiconductor fin and the second semiconductor fin.

### Claim 16

A method comprising:
forming a semiconductor fin on a doped substrate;
forming an isolation region on the doped substrate, the isolation region surrounding the semiconductor fin;
implanting dopants into the semiconductor fin;
after implanting dopants into the semiconductor fin, recessing the isolation region to expose at least a portion of the semiconductor fin;
performing a dry etch process on the exposed portion of the semiconductor fin;
after performing the dry etch process, epitaxially growing a capping layer on a top surface and sidewalls of the semiconductor fin;
forming a gate dielectric on the capping layer;
forming a gate electrode on the gate dielectric;
forming a source region in the semiconductor fin; and
forming a drain region in the semiconductor fin, the source region being on an opposite side of the gate electrode than the drain region, the capping layer extending across the top surface of the semiconductor fin from the source region to the drain region.

### Claim 17 (depends on 16)

The method of claim 16, wherein the implanting dopants into the semiconductor fin causes twin plane defects in the semiconductor fin, wherein the capping layer is epitaxially grown over the twin plane defects.

### Claim 18 (depends on 16)

The method of claim 16, wherein a bottom surface of the capping layer adjoins a top surface of the isolation region.

### Claim 19 (depends on 16)

The method of claim 16 further comprising:
after implanting dopants into the semiconductor fin and before recessing the isolation region, performing an anneal process on the semiconductor fin.