# US 9,520,501 B2 · Vertical super-thin body semiconductor on dielectric wall devices and methods of their fabrication

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- Number: US 9,520,501 B2
- Document ID: US9520501B2
- Status: Granted
- Kind: B2
- Application number: 14/729,917
- Filed: 2015-06-03
- Published: 2015-10-01
- Granted: 2016-12-13
- Earliest claimed: 2012-10-12
- Assignees: Finscale Inc.
- Applicants: FinScale Inc.
- Inventors: Viktor I. Koldiaev; Rimma A. Pirogova
- Web page: https://patentgrep.com/patent/US9520501B2

## CPC

- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10B 10/125: {the MOSFET being a thin film transistor [TFT]}
- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6758: {characterised by the insulating substrates}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/834: {comprising FinFETs}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 86/011: {comprising FinFETs}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D 86/215: {comprising FinFETs}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/43: Layouts of interconnections
- H10B 10/12: {comprising a MOSFET load element}
- H10B 12/056: {the transistor being a FinFET}
- H10B 12/36: {the transistor being a FinFET}
- H10B 41/30: characterised by the memory core region
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present invention is a semiconductor device comprising a semiconducting low doped vertical super-thin body (VSTB) formed on Dielectric Body Wall (such as STI-wall as isolating substrate) having the body connection to bulk semiconductor wafer on the bottom side, isolation on the top side, and the channel, gate dielectric, and gate electrode on opposite to STI side surface. The body is made self-aligned to STI hard mask edge allowing tight control of body thickness. Source and Drain are made by etching holes vertically in STI at STI side of the body and filling with high doped crystalline or poly-Si appropriately doped with any appropriate silicides/metal contacts or with Schottky barrier Source/Drain. Gate first or Gate last approaches can be implemented. Many devices can be fabricated in single active area with body isolation between the devices by iso-plugs combined with gate electrode isolation by iso-trenches. The body can be made as an isolated nano-plate or set nano-wire MOSFET's on the STI wall to form VSTB SOI devices.

## Claims

### Claim 1

A transistor device, comprising: a semiconductor substrate; a dielectric body, the dielectric body embedded in the semiconductor substrate and including sidewalls; and
a semiconducting vertical super-thin body (“VSTB”) formed from the semiconductor substrate and supported by at least the sidewall of the dielectric body, the VSTB having two vertical faces, a first face and a second face, the first face in contact with the sidewall of the dielectric body, the VSTB serving as a channel for the transistor device;
at least one source and drain electrode pair (electrode pair), comprising a source electrode and a drain electrode formed in isolated holes made in the dielectric body, wherein each source electrode and each drain electrode physically contact the first face of the VSTB.

### Claim 2 (depends on 1)

The transistor device of claim 1, wherein the VSTB thickness is less than 10 nm.

### Claim 3 (depends on 1)

The transistor device of claim 1, wherein the VSTB additionally serves as a channel for neighboring transistor devices.

### Claim 4

A transistor device, comprising:
a semiconductor substrate;
a dielectric body, the dielectric body embedded in the semiconductor substrate and including sidewalls;
a semiconducting vertical super-thin body (“VSTB”) formed from the semiconductor substrate and supported by at least the sidewall of the dielectric body, the VSTB having two vertical faces, a first face and a second face, the first face in contact with the sidewall of the dielectric body, the VSTB serving as a channel for the transistor device;
at least one source and drain electrode pair (electrode pair), comprising a source electrode and a drain electrode formed in isolated holes made in the dielectric body, wherein each source electrode and each drain electrode physically contact the first face of the VSTB; and
a gate, the gate in contact with either the first or the second face.

### Claim 5 (depends on 4)

The transistor device as recited in claim 4, wherein the second face of the VSTB is supported by a second dielectric body, the second dielectric body associated with a neighboring transistor device formed in the semiconductor substrate.

### Claim 6 (depends on 4)

The transistor device as recited in claim 4, wherein the gate contacts the second face and the VSTB is wrapped around the gate such that the second face of the VSTB makes contact with the gate on all sides in at least a 2D plane, and including at least a second source and drain electrode pair and arranged such that at least two transistors are created using the single gate.

### Claim 7 (depends on 4)

The transistor device as recited in claim 4, wherein the VSTB is a first VSTB and the dielectric body is a first dielectric body, and further comprising:
a second VSTB; and
a second dielectric body;
wherein the second face of the second VSTB contacts an opposite side of the gate than contacts the first VSTB, and the second VSTB includes at least one additional electrode pair, thereby creating a second transistor mirroring the transistor device and both the second transistor and the transistor device using said gate.

### Claim 8 (depends on 4)

The transistor device as recited in claim 4, wherein said semiconductor substrate is further electrically and physically connected to multiple VSTBs in a single active area with isolated source and drain electrodes and where gates are separated by forming an isolation trench through the gate stack and filled with a dielectric material.

### Claim 9 (depends on 4)

The transistor device of claim 4, wherein the semiconductor substrate used is a silicon-on-isolator such that the VSTB is separated from the semiconductor substrate electrically by the buried oxide layer and the gate-to-substrate isolation layer is the isolator layer in the semiconductor substrate.

### Claim 10 (depends on 4)

The transistor device of claim 4, wherein the semiconductor substrate has multiple alternating layers of semiconductor material and a dielectric or a second semiconductor material with a substantial difference in lateral etch rate such that when formed, the VSTB comprises nanowires parallel to the substrate.

### Claim 11

An array of transistors formed on a single semiconductor substrate, each transistor in the array comprising:
a dielectric body, the dielectric body embedded in the semiconductor substrate and including sidewalls;
a semiconducting vertical super-thin body (“VSTB”) formed from the semiconductor substrate and supported by at least the sidewall of the dielectric body, the VSTB having two vertical faces, a first face and a second face, the first face in contact with the sidewall of the dielectric body, the VSTB serving as a channel for the transistor device;
at least one source and drain electrode pair (electrode pair), comprising a source electrode and a drain electrode formed in isolated holes made in the dielectric body, wherein each source electrode and each drain electrode physically contact the first face of the VSTB; and
a gate, the gate in contact with either the first or the second face.

### Claim 12 (depends on 11)

The transistor array of claim 11, each transistor in the array further comprising:
a memory stack which is formed on either the first face or the second face of the VSTB, between the gate and the VSTB, thereby enabling the transistor device to be used as a memory device.

### Claim 13 (depends on 11)

The transistor array as recited in claim 11, further comprising:
a metal-zero interconnect electrically connected to the gate but electrically isolated from the electrodes pair, the metal-zero interconnect electrically connecting the gate of a plurality of transistors in the array of transistors, thereby configuring the gate of neighboring transistor devices act as a common gate.

### Claim 14 (depends on 11)

The transistor array as recited in claim 11, further comprising:
a metal-zero interconnect electrically connected to either the source electrode or drain electrode and electrically isolated from other electrode and provides an electrical connection to a corresponding electrode on a neighboring transistor.

### Claim 15 (depends on 11)

The transistor array of claim 11, further comprising:
isolation plugs, wherein the isolation plugs sever the VSTB on either side of each transistor in the array such that at least a plurality of the transistors in the array do not share a common VSTB.

### Claim 16 (depends on 12)

The transistor array of claim 12, wherein the transistor array is comprised of cells, the transistor array is configured as a circuit to act as a NOR flash memory array and further comprising:
bit lines where source and drain electrodes are common for every cell connected to the bit lines and gates purposed as word lines.

### Claim 17 (depends on 12)

The transistor array of claim 12, wherein the array is configured as a circuit to act as a NAND flash memory array.

### Claim 18 (depends on 12)

The transistor array of claim 12, wherein groups of at least six transistors in the array are wired as a circuit and function as a SRAM array cell.