# US 9,520,497 B2 · Semiconductor devices including a stressor in a recess and methods of forming the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 9,520,497 B2
- Document ID: US9520497B2
- Status: Granted
- Kind: B2
- Application number: 14/951,932
- Filed: 2015-11-25
- Published: 2016-03-17
- Granted: 2016-12-13
- Earliest claimed: 2012-11-22
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Dong-Suk Shin; Chul-Woong Lee; Hoi-Sung Chung; Young-Tak Kim; Nae-In Lee
- Inventors: Dong-Suk Shin; Chul-Woong Lee; Hoi-Sung Chung; Young-Tak Kim; Nae-In Lee
- Web page: https://patentgrep.com/patent/US9520497B2

## CPC

- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 30/0223: {having source and drain regions or source and drain extensions self-aligned to sides of the gate}
- H10D 30/027: {of lateral single-gate IGFETs}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 30/608: {having non-planar bodies, e.g. having recessed gate electrodes}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/10: Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/405: {Orientations of crystalline planes}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/834: further characterised by the dopants
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/0133: {Manufacturing common source or drain regions between multiple IGFETs}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0184: {Manufacturing their gate sidewall spacers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10P 14/27: {using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials}
- H10P 50/642: {Chemical etching}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate;
a gate structure on the substrate;
a spacer adjacent to a sidewall of the gate structure; and
a semiconductor layer disposed adjacent to the sidewall of the gate structure and disposed in a recess that extends below an upper surface of the substrate, the semiconductor layer being a strain-inducing pattern,
wherein a portion of the recess underlies the gate structure,
wherein the semiconductor layer comprises a portion that is in the substrate and directly contacts a lower surface of the spacer, and an interface between the spacer and the portion of the semiconductor layer is not below a lower surface of the gate structure, and
wherein the portion of the semiconductor layer comprises a first sidewall that has a linear shape and directly contacts the lower surface of the spacer, and the first sidewall of the portion of the semiconductor layer forms an acute angle with the lower surface of the spacer and extends beyond the sidewall of the gate structure.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the interface between the spacer and the portion of the semiconductor layer is coplanar with the lower surface of the gate structure.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the gate structure includes a gate dielectric and a gate electrode over the gate dielectric.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the gate structure comprises a gate electrode, a first gate dielectric layer, and a second gate dielectric layer comprising a high-K dielectric material, and
the portion of the recess underlies the gate electrode, the first gate dielectric layer or the second gate dielectric layer.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the portion of the semiconductor layer comprises a second sidewall that has a linear shape and directly contacts the first sidewall of the portion of the semiconductor layer,
wherein the first sidewall and the second sidewall converge at a convergence interface, and
wherein the gate structure overlaps the convergence interface.

### Claim 6 (depends on 3)

The semiconductor device of claim 3, wherein the spacer contacts the gate electrode.

### Claim 7 (depends on 3)

The semiconductor device of claim 3, further comprising at least one nitride layer between the spacer and the gate electrode.

### Claim 8 (depends on 3)

The semiconductor device of claim 3, wherein the gate structure includes a high-K dielectric material.

### Claim 9 (depends on 5)

The semiconductor device of claim 5, further comprising a lightly doped drain (LDD) region in the substrate, wherein the convergence interface directly contacts the LDD region.

### Claim 10 (depends on 5)

The semiconductor device of claim 5, wherein the portion of the semiconductor layer is spaced apart from the lower surface of the gate structure, and
wherein a distance between the lower surface of the gate structure and the convergence interface is from 3 nm to 7 nm.

### Claim 11 (depends on 8)

The semiconductor device of claim 8, wherein the spacer contacts the gate electrode.

### Claim 12 (depends on 8)

The semiconductor device of claim 8, further comprising at least one nitride layer between the spacer and the gate electrode.

### Claim 13 (depends on 9)

The semiconductor device of claim 9, wherein the LDD region comprises a first impurity having a p-conductivity type and phosphorous (P).

### Claim 14 (depends on 9)

The semiconductor device of claim 9, wherein the LDD region comprises a first impurity having a p-conductivity type, and the spacer comprises a second impurity having an n-conductivity type.

### Claim 15 (depends on 13)

The semiconductor device of claim 13, wherein a phosphorous concentration in the LDD region is in a range of from 5E18 to 1E19 atoms/cm3.

### Claim 16

A semiconductor device comprising:
a substrate;
a gate structure including a gate dielectric layer over the substrate and a gate electrode over the gate dielectric layer;
a spacer adjacent to a sidewall of the gate electrode; and
a semiconductor layer disposed adjacent to the gate structure and disposed in a recess that extends below an upper surface of the substrate, the semiconductor layer being a strain-inducing pattern,
wherein a portion of the recess underlies the gate structure,
wherein the spacer directly contacts a first portion of the semiconductor layer above a lower surface of the gate dielectric layer,
wherein the semiconductor layer comprises a second portion in the substrate, and the second portion of the semiconductor layer comprises a first sidewall that directly contacts the upper surface of the substrate and has a linear shape and a second sidewall that directly contacts the first sidewall and has a linear shape,
wherein the first and second sidewalls of the second portion of the semiconductor layer are slanted with respect to the upper surface of the substrate and converge at a convergence interface, and
wherein the gate electrode overlaps the convergence interface.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein an interface between the spacer and the semiconductor layer located under the spacer is not below a lower surface of the gate structure.

### Claim 18 (depends on 16)

The semiconductor device of claim 16, wherein the first and second sidewalls of the second portion of the semiconductor layer are in the same crystal plane.

### Claim 19 (depends on 16)

The semiconductor device of claim 16, further comprising a lightly doped drain (LDD) region in the substrate, wherein the LDD region comprises a first impurity having a p-conductivity type and phosphorous (P).

### Claim 20 (depends on 19)

The semiconductor device of claim 19, wherein the convergence interface directly contacts the LDD region.

### Claim 21

A method for forming a semiconductor device, the method comprising:
forming a gate structure over a semiconductor substrate, the gate structure including a gate insulating layer and a gate electrode over the gate insulating layer;
forming a first spacer over the semiconductor substrate;
forming a second spacer along a sidewall of the gate structure;
forming a recess extending into the semiconductor substrate adjacent to the gate structure, wherein the recess comprises a notched portion of the semiconductor substrate that underlies the gate structure and is spaced apart from the gate structure, the notched portion comprises a first sidewall directly contacting an upper surface of the semiconductor substrate and a second sidewall directly contacting the first sidewall of the recess, each of the first and second sidewalls has a linear shape, and the gate electrode overlaps a portion of the recess;
removing at least a portion of the first spacer; and
filling the recess with a stressor that directly contacts a bottom surface of the first spacer,
wherein a contacting interface between the stressor and the bottom surface of the first spacer is not below a lower surface of the gate insulating layer, and
the stressor is a strain-inducing pattern.

### Claim 22 (depends on 21)

The method of claim 21, wherein the forming the recess includes performing an anisotropic etch process, whereby the recess extends under the first spacer.

### Claim 23 (depends on 21)

The method of claim 21, further comprising forming a nitride layer along the sidewall of the gate structure.

### Claim 24 (depends on 21)

The method of claim 21, wherein the first sidewall and the second sidewall of the recess converge at a convergence interface, and
wherein a distance between the lower surface of the gate insulating layer and the convergence interface is from 3 nm to 7 nm.

### Claim 25 (depends on 21)

The method of claim 21, further comprising forming a lightly doped drain (LDD) region in the substrate before forming the recess, wherein the first sidewall and the second sidewall of the recess exposes the LDD region.

### Claim 26

A semiconductor device comprising:
a substrate;
a gate structure disposed on the substrate;
a spacer adjacent to a sidewall of the gate structure; and
a semiconductor layer disposed adjacent to the gate structure and disposed in a recess that extends below an upper surface of the substrate, the semiconductor layer being a strain-inducing pattern,
wherein a portion of the recess underlies the gate structure, and
wherein an interface between the spacer and the semiconductor layer located under the spacer is coplanar with a lower surface of the gate structure,
wherein the semiconductor layer in the substrate comprises a first portion contacting the spacer and a second portion below the first portion,
wherein the first portion comprises a first sidewall having a linear shape and has a width gradually increasing with a depth of the recess, and the second portion comprises a second sidewall having a linear shape and has a width gradually decreasing with the depth of the recess.

### Claim 27 (depends on 26)

The semiconductor device of claim 26, wherein the gate structure includes a gate dielectric and a gate electrode over the gate dielectric.

### Claim 28 (depends on 26)

The semiconductor device of claim 26, wherein the semiconductor layer is at least partially disposed directly below the gate structure.

### Claim 29 (depends on 26)

The semiconductor device of claim 26, further comprising a lightly doped drain (LDD) region in the substrate, wherein the second portion of the semiconductor layer contacts the LDD region.

### Claim 30 (depends on 29)

The semiconductor device of claim 29, wherein the LDD region comprises a first impurity having a p-conductivity type, and the spacer comprises phosphorous (P).