# US 9,520,496 B2 · Charge carrier transport facilitated by strain

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- Number: US 9,520,496 B2
- Document ID: US9520496B2
- Status: Granted
- Kind: B2
- Application number: 14/585,474
- Filed: 2014-12-30
- Published: 2016-06-30
- Granted: 2016-12-13
- Earliest claimed: 2014-12-30
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Anirban Basu; Guy M. Cohen
- Web page: https://patentgrep.com/patent/US9520496B2

## CPC

- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/405: {Orientations of crystalline planes}
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 62/85: being Group III-V materials, e.g. GaAs
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10P 14/3421: {Arsenides}
- H10P 50/646: {of Group III-V materials}
- H10D 62/852: being Group III-V materials comprising three or more elements, e.g. AlGaN or InAsSbP
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/2909: {Phosphides}
- H10P 14/3442: {N-type}
- H10P 14/3444: {P-type}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure and formation thereof. The semiconductor structure has a first semiconductor layer with a first lattice structure and a second epitaxial semiconductor layer that is lattice-matched with the first semiconductor layer. At least two source/drain regions, which have a second lattice structure, penetrate the second semiconductor layer and contact the first semiconductor layer. A portion of the second semiconductor layer is between the source/drain regions and has a degree of uniaxial strain that is based, at least in part, on a difference between the first lattice structure and the second lattice structure.

## Claims

### Claim 1

A semiconductor structure comprising:
a first semiconductor layer with a first lattice structure;
a second semiconductor layer that is lattice-matched with the first semiconductor layer, wherein the second semiconductor layer is epitaxial with the first semiconductor layer; and
at least two source/drain regions with a second lattice structure, wherein the source/drain regions penetrate the second semiconductor layer and contact the first semiconductor layer, wherein a portion of the second semiconductor layer is between the source/drain regions, wherein the portion has a degree of uniaxial strain that is based, at least in part, on a difference between the first lattice structure and the second lattice structure.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the first semiconductor layer is further comprised of a semi-insulating semiconductor material.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein one or both of: the second semiconductor layer and the source/drain regions are further comprised of compound semiconductors.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein one or both of: the second semiconductor layer and the source/drain regions are further comprised of ternary semiconductors.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein one or both of: the second semiconductor layer and the source/drain regions are further comprised of III-V semiconductors.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, wherein one or both of: the second semiconductor layer and the source/drain regions include indium.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, wherein one or both of: the second semiconductor layer and the source/drain regions are further comprised of alloys of indium arsenide and gallium arsenide.

### Claim 8 (depends on 1)

The semiconductor structure of claim 1, wherein the second semiconductor layer is further comprised of In0.53Ga0.47As and the source/drain regions are further comprised of InyGa(1-y)As, and wherein y has a range between approximately 0.53 and 1.

### Claim 9 (depends on 1)

The semiconductor structure of claim 1, wherein the second semiconductor layer is further comprised of In0.53Ga0.47As and the source/drain regions are further comprised of InyGa(1-y)As, and wherein y has a range between 0 and approximately 0.53.

### Claim 10

A method of forming a semiconductor structure comprising:
forming a layer of a first semiconductor material on top of a layer of a semi-insulating semiconductor material, wherein the first semiconductor material and the semi-insulating semiconductor material are lattice-matched;
etching the layer of first semiconductor material to a depth that, at least, exposes the semi-insulating semiconductor material and forms a semiconductor channel region, wherein the semiconductor channel region has a first end and a second end; and
forming a first source/drain region at the first end of the semiconductor channel region and a second source/drain region at the second end of the semiconductor channel region, wherein the first source/drain region and the second source/drain region are further comprised of a second semiconductor material, wherein the second semiconductor material is lattice-mismatched to the first semiconductor material and to the semi-insulating semiconductor material.

### Claim 11 (depends on 10)

The method of claim 10, wherein the etching step provides an isotropic etch.

### Claim 12 (depends on 10)

The method of claim 10 further comprising:
fabricating a gate structure on top of the layer of the first semiconductor material.

### Claim 13 (depends on 10)

The method of claim 10 further comprising:
fabricating a gate structure on top of the semiconductor channel region such that the gate structure is between the first source/drain region and the second source/drain region.

### Claim 14 (depends on 10)

The method of claim 10, wherein one or both of the first semiconductor material and the second semiconductor material are further comprised of compound semiconductors.

### Claim 15 (depends on 10)

The method of claim 10, wherein one or both of the first semiconductor material and the second semiconductor material are further comprised of III-V semiconductors.

### Claim 16 (depends on 10)

The method of claim 10, wherein one or both of the first semiconductor material and the second semiconductor material include indium.

### Claim 17 (depends on 10)

The method of claim 10, wherein one or both of the first semiconductor material and the second semiconductor material are further comprised of alloys of indium arsenide and gallium arsenide.

### Claim 18

A semiconductor structure comprising:
a semi-insulating semiconductor layer composed of a doped indium phosphide material;
a semiconductor layer composed of In0.53Ga0.47As, wherein the semiconductor layer is epitaxial with the semi-insulating semiconductor layer, wherein the semiconductor layer is lattice-matched with the semi-insulating semiconductor layer; and
at least two source/drain regions composed of InyGa(1-y)As, wherein y has a range between 0 and 1, wherein the source/drain regions penetrate the semiconductor layer and contact the semi-insulating semiconductor layer, wherein the source/drain regions are lattice-mismatched with the semi-insulating semiconductor layer and the semiconductor layer, wherein a portion of the semiconductor layer is between source/drain regions, wherein the portion has a degree of uniaxial strain that is based, at least in part, on the lattice-mismatch between the source/drain regions and both the semi-insulating semiconductor layer and the semiconductor layer.

### Claim 19 (depends on 18)

The semiconductor structure of claim 18, wherein y has a range between approximately 0.53 and 1.

### Claim 20 (depends on 18)

The semiconductor structure of claim 18, wherein y has a range between 0 and approximately 0.53.