# US 9,520,495 B2 · Transistor including a stressed channel, a method for fabricating the same, and an electronic device including the same

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- Number: US 9,520,495 B2
- Document ID: US9520495B2
- Status: Granted
- Kind: B2
- Application number: 14/863,362
- Filed: 2015-09-23
- Published: 2016-01-14
- Granted: 2016-12-13
- Earliest claimed: 2013-11-11
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Yun-Hyuck Ji
- Web page: https://patentgrep.com/patent/US9520495B2

## CPC

- H10D 30/794: {comprising conductive materials, e.g. silicided source, drain or gate electrodes}
- H10D 30/0215: {using self-aligned selective metal deposition simultaneously on gate electrodes and the source regions or drain regions}
- H10D 30/0223: {having source and drain regions or source and drain extensions self-aligned to sides of the gate}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/751: {having composition variations in the channel regions}
- H10D 30/798: {being provided in or under the channel regions}
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10D 64/661: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation (having lateral variation in the gate structure H10D64/671)}
- H10D 64/663: {the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a first channel, a second channel, a first strained gate electrode including a first lattice-mismatched layer for applying a first stress to the first channel, and a second strained gate electrode including a second lattice-mismatched layer for applying a second stress to the second channel.

## Claims

### Claim 1

A method for fabricating a semiconductor device, the method comprising:
preparing a substrate which includes a first transistor region and a second transistor region;
forming a first strained gate electrode which includes a first lattice-mismatched crystalline silicon layer disposed over the first transistor region; and
forming a second strained gate electrode which includes a second lattice-mismatched crystalline silicon layer disposed over the second transistor region,
wherein the forming of the first lattice-mismatched crystalline silicon layer comprises:
forming an arsenic-doped crystalline silicon layer by doping only arsenic; and
forming an undoped crystalline silicon layer disposed over the arsenic-doped crystalline silicon layer, the undoped crystalline silicon layer being undoped with arsenic, and
wherein the forming of the second lattice-mismatched crystalline silicon layer comprises:
forming a boron-doped crystalline silicon layer; and
forming a germanium-doped crystalline silicon layer, the germanium-doped crystalline silicon layer being disposed over the boron-doped crystalline silicon layer.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the forming of the arsenic-doped crystalline silicon layer and the undoped crystalline silicon layer comprises:
forming a gate dielectric layer over the substrate;
forming an amorphous silicon layer over the gate dielectric layer;
doping arsenic into a lower portion of the amorphous silicon layer to form a stacked structure of a doped amorphous silicon layer and an undoped amorphous silicon layer; and
performing an annealing process on the stacked structure to convert the doped amorphous silicon layer and the undoped amorphous silicon layer into the arsenic-doped crystalline silicon layer and the undoped crystalline silicon layer, respectively, which are included in the first lattice-mismatched crystalline silicon layer.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the forming of the boron-doped crystalline silicon layer and the germanium-doped crystalline silicon layer comprises:
forming a gate dielectric layer over the substrate;
forming an amorphous silicon layer over the gate dielectric layer;
doping boron into a lower portion of the amorphous silicon layer to form a first doped amorphous silicon layer;
doping germanium into a upper portion of the amorphous silicon layer to form a second doped amorphous silicon layer over the first doped amorphous silicon layer; and
performing an annealing process on the first and second amorphous silicon layers to convert the first doped amorphous silicon layer and the second doped amorphous silicon layer into the boron-doped crystalline silicon layer and the germanium-doped crystalline silicon layer, respectively, which are included in the second lattice-mismatched crystalline silicon layer.

### Claim 4 (depends on 1)

The method according to claim 1, wherein the forming of the arsenic-doped crystalline silicon layer and the undoped crystalline silicon layer and the forming of the boron-doped crystalline silicon layer and the germanium-doped crystalline silicon layer comprise:
forming an amorphous silicon layer over the substrate;
masking the second transistor region;
doping arsenic into a lower portion of the amorphous silicon layer formed over the first transistor region to form a first stacked structure of a first doped amorphous silicon layer doped with arsenic and an amorphous silicon layer that is not doped with arsenic;
masking the first transistor region;
sequentially doping boron and germanium into a lower portion and an upper portion of the amorphous silicon layer formed over the second transistor region, respectively, to form a second stacked structure of a second doped amorphous silicon layer doped with boron and a third doped amorphous silicon layer doped with germanium;
patterning the first stacked structure and the second stacked structure to form a first gate electrode and a second gate electrode, respectively; and
converting the first gate electrode and the second gate electrode into the first lattice-mismatched crystalline silicon layer, which includes the arsenic-doped crystalline silicon layer and the undoped crystalline silicon layer, and the second lattice-mismatched crystalline silicon layer, which includes the boron-doped crystalline silicon layer and the germanium-doped crystalline silicon layer, respectively.

### Claim 5 (depends on 4)

The method according to claim 4, after forming the first gate electrode and the second gate electrode, further comprising:
implanting impurities into the substrate to form source regions and drain regions; and
performing an activation annealing process on a resultant structure including the source regions and the drain regions,
wherein the first gate electrode and the second gate electrode are converted into the first lattice-mismatched crystalline silicon layer and the second lattice-mismatched crystalline silicon layer, respectively, by the activation annealing process.

### Claim 6 (depends on 1)

The method according to claim 1, after forming the first strained gate electrode and the second strained gate electrode, further comprising:
forming a metal silicide layer over the first lattice-mismatched crystalline silicon layer and the second lattice-mismatched crystalline silicon layer.

### Claim 7 (depends on 1)

The method according to claim 1, wherein the first transistor region comprises a first channel, the first channel being converted into a tensile stressed channel by a tensile stress applied from the first strained gate electrode, and the second transistor region comprises a second channel, the second channel being converted into a compressive stressed channel by a compressive stress applied from the second strained gate electrode.