# US 9,520,494 B2 · Vertical non-planar semiconductor device for system-on-chip (SoC) applications

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- Number: US 9,520,494 B2
- Document ID: US9520494B2
- Status: Granted
- Kind: B2
- Application number: 14/913,326
- Filed: 2013-09-26
- Published: 2016-07-21
- Granted: 2016-12-13
- Earliest claimed: 2013-09-26
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Chia-Hong Jan; Walid M. Hafez; Curtis Tsai; Jeng-Ya D. Yeh; Joodong Park
- Web page: https://patentgrep.com/patent/US9520494B2

## CPC

- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/6728: {Vertical TFTs}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 86/00: Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Vertical non-planar semiconductor devices for system-on-chip (SoC) applications and methods of fabricating vertical non-planar semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a substrate, the semiconductor fin having a recessed portion and an uppermost portion. A source region is disposed in the recessed portion of the semiconductor fin. A drain region is disposed in the uppermost portion of the semiconductor fin. A gate electrode is disposed over the uppermost portion of the semiconductor fin, between the source and drain regions.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor fin disposed above a substrate, the semiconductor fin having a recessed portion and an uppermost portion;
a source region disposed in the recessed portion of the semiconductor fin;
a drain region disposed in the uppermost portion of the semiconductor fin; and
a gate electrode disposed over the uppermost portion of the semiconductor fin, between the source and drain regions.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising a substantially vertical channel region disposed between the source and drain regions and electrically controlled by the gate electrode.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the drain region comprises an upper doped region of a first conductivity type disposed in the uppermost region of the semiconductor fin, and the source region comprises a lower doped region of the first conductivity type disposed in the semiconductor fin below the recessed portion of the semiconductor fin.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the semiconductor fin is disposed on a bulk semiconductor substrate, and wherein the lower doped region of the first conductivity type is further disposed in an upper portion of the bulk semiconductor substrate, the semiconductor device further comprising:
a doped region of a second, opposite, conductivity type disposed in the bulk semiconductor substrate below, and in contact with, the lower doped region of the first conductivity type.

### Claim 5 (depends on 3)

The semiconductor device of claim 3, wherein the semiconductor device is an N-type device, and wherein the first conductivity type is N-type.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the drain region comprises a first epitaxial region disposed on the uppermost portion of the semiconductor fin, and the source region comprises a second epitaxial region disposed on the recessed portion of the semiconductor fin.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the semiconductor fin comprises another uppermost portion, and wherein the recessed portion of the semiconductor fin is disposed between the uppermost portion and the other uppermost portion, the semiconductor device further comprising:
a second drain region disposed in the other uppermost portion of the semiconductor fin; and
a second gate electrode disposed over the other uppermost portion of the semiconductor fin, between the source region and the second drain region.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the semiconductor device is a tri-gate device.

### Claim 9

An N-type vertical fin-FET device, comprising:
a silicon fin disposed on a bulk silicon substrate, the silicon fin having a recessed portion and an uppermost portion;
a source region disposed in the recessed portion of the silicon fin;
a drain region disposed in the uppermost portion of the silicon fin;
an N-type gate electrode disposed over the uppermost portion of the silicon fin, between the source and drain regions; and
a substantially vertical channel region disposed between the source and drain regions and electrically controlled by the N-type gate electrode.

### Claim 10 (depends on 9)

The N-type vertical fin-FET device of claim 9, wherein the drain region comprises an upper N-type doped region disposed in the uppermost region of the silicon fin, and the source region comprises a lower N-type doped region disposed in the silicon fin, below the recessed portion of the silicon fin, and in an upper portion of the bulk silicon substrate.

### Claim 11 (depends on 10)

The N-type vertical fin-FET device of claim 10, further comprising:
a P-type doped region disposed in the bulk silicon substrate below, and in contact with, the lower N-type doped region.

### Claim 12 (depends on 10)

The N-type vertical fin-FET device of claim 10, wherein the drain region further comprises a first N-type epitaxial silicon region disposed on the uppermost portion of the silicon fin, and the source region further comprises a second N-type epitaxial silicon region disposed on the recessed portion of the silicon fin.

### Claim 13 (depends on 9)

The N-type vertical fin-FET device of claim 9, wherein the silicon fin comprises another uppermost portion, and wherein the recessed portion of the silicon fin is disposed between the uppermost portion and the other uppermost portion, the N-type vertical fin-FET device further comprising:
a second drain region disposed in the other uppermost portion of the silicon fin; and
a second N-type gate electrode disposed over the other uppermost portion of the silicon fin, between the source region and the second drain region.

### Claim 14 (depends on 9)

The N-type vertical fin-FET device of claim 9, wherein the N-type vertical fin-FET device is a tri-gate device.

### Claim 15

A method of fabricating a semiconductor device, the method comprising:
forming a semiconductor fin above a substrate;
forming a subdoping region of a first conductivity type in the bottom of the semiconductor fin;
forming an upper doping region of the first conductivity type in the top of the semiconductor fin, the upper doping region separated from the subdoping region;
forming a gate electrode over the semiconductor fin;
etching the semiconductor fin to provide a recessed portion and an uppermost portion of the semiconductor fin;
forming a source region in the recessed portion of the semiconductor fin, the source region comprising at least a portion of the subdoping region; and
forming a drain region in the uppermost portion of the semiconductor fin, the drain region comprising at least a portion of the upper doping region, wherein the gate electrode is between the source and drain regions.

### Claim 16 (depends on 15)

The method of claim 15, wherein forming the semiconductor fin comprises etching the semiconductor fin in the substrate, the method further comprising:
forming a doped region of a second, opposite, conductivity type in the substrate below, and in contact with, the subdoping region of the first conductivity type.

### Claim 17 (depends on 15)

The method of claim 15, further comprising:
prior to forming the gate electrode, forming a shallow trench isolation (STI) region around the semiconductor fin and above the substrate, wherein the semiconductor fin protrudes above the STI region.

### Claim 18 (depends on 15)

The method of claim 15, wherein forming the source region further comprises forming a first epitaxial region of the first conductivity type on the recessed portion of the semiconductor fin, and wherein forming the drain region further comprises forming a second epitaxial region of the first conductivity type on a portion of the uppermost portion of the semiconductor fin.

### Claim 19 (depends on 15)

The method of claim 15, wherein forming the subdoping region comprises using a solid-state doping source layer.

### Claim 20 (depends on 15)

The method of claim 15, wherein forming the gate electrode comprises forming a dummy gate electrode, the method further comprising:
forming a permanent gate electrode by a replacement gate process.

### Claim 21 (depends on 15)

The method of claim 15, further comprising:
forming an N-type vertical fin-FET device from the source region, the drain region, and the gate electrode.

### Claim 22 (depends on 21)

The method of claim 21, wherein forming the N-type vertical fin-FET device comprises forming a tri-gate device.