# US 9,520,493 B1 · High voltage integrated circuits having improved on-resistance value and improved breakdown voltage

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- Number: US 9,520,493 B1
- Document ID: US9520493B1
- Status: Granted
- Kind: B1
- Application number: 15/130,790
- Filed: 2016-04-15
- Granted: 2016-12-13
- Earliest claimed: 2015-11-23
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Dae Hoon Kim; Se Kyung Oh
- Web page: https://patentgrep.com/patent/US9520493B1

## CPC

- H10D 30/0281: {of lateral DMOS [LDMOS] FETs}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 64/111: {Field plates}
- H10D 64/516: {the thicknesses being non-uniform}
- H10D 62/307: {the doping variations being parallel to the channel lengths}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A high voltage integrated device includes a semiconductor layer having a first conductivity, a source region having a second conductivity and a drift region having the second conductivity which are disposed in the semiconductor layer and spaced apart from each other by a channel region, a drain region having the second conductivity and disposed in the drift region, a gate insulation layer disposed over the channel region, a first field insulation layer and a second field insulation layer which are disposed over the drift region and between the channel region and the drain region, wherein the first field insulation layer and the second field insulation layer are spaced apart from each other, an insulation layer disposed over the drift region and located between the first and second field insulation layers, and a gate electrode disposed over the gate insulation layer, the first field insulation layer, the insulation layer, and the second field insulation layer, wherein the first field insulation layer is adjacent to the channel region and the second field insulation layer is adjacent to the drain region.

## Claims

### Claim 1

A high voltage integrated device comprising:
a semiconductor layer having a first conductivity;
a source region having a second conductivity and a drift region having the second conductivity which are disposed in the semiconductor layer and spaced apart from each other by a channel region;
a drain region having the second conductivity and disposed in the drift region;
a gate insulation layer disposed over the channel region;
a first field insulation layer and a second field insulation layer which are disposed over the drift region and between the channel region and the drain region, wherein the first field insulation layer and the second field insulation layer are spaced apart from each other;
an insulation layer disposed over the drift region and located between the first and second field insulation layers; and
a gate electrode disposed over the gate insulation layer, the first field insulation layer, the insulation layer, and the second field insulation layer,
wherein the first field insulation layer is adjacent to the channel region and the second field insulation layer is adjacent to the drain region.

### Claim 2 (depends on 1)

The high voltage integrated device of claim 1, further comprising:
a body region having the first conductivity, disposed in the semiconductor layer, and surrounding the source region,
wherein the body region is spaced apart from the drift region.

### Claim 3 (depends on 2)

The high voltage integrated device of claim 2, wherein the channel region includes:
a first channel region defined in an upper portion of the body region and between the source region and the semiconductor layer; and
a second channel region defined in an upper portion of the semiconductor layer and between the body region and the drift region.

### Claim 4 (depends on 1)

The high voltage integrated device of claim 1, wherein a top surface of the drift region is coplanar with a top surface of the channel region.

### Claim 5 (depends on 1)

The high voltage integrated device of claim 1, wherein the first and second field insulation layers have substantially the same thickness.

### Claim 6 (depends on 1)

The high voltage integrated device of claim 1, wherein a first sidewall of the first field insulation layer is in direct contact with a sidewall of the gate insulation layer.

### Claim 7 (depends on 6)

The high voltage integrated device of claim 6, wherein the first sidewall of the first field insulation layer is aligned with a first sidewall of the drift region, and
wherein the first sidewall of the drift region is in contact with the channel region.

### Claim 8 (depends on 6)

The high voltage integrated device of claim 6, wherein a first sidewall of the insulation layer is in direct contact with a second sidewall of the first field insulation layer, and
wherein a second sidewall of the insulation layer is in direct contact with a first sidewall of the second field insulation layer.

### Claim 9 (depends on 8)

The high voltage integrated device of claim 8, wherein a second sidewall of the second field insulation layer is aligned with a second sidewall of the drain region.

### Claim 10 (depends on 1)

The high voltage integrated device of claim 1, wherein each of the first and second field insulation layers have a sloped sidewall profile.

### Claim 11 (depends on 1)

The high voltage integrated device of claim 1, wherein a length of the first field Insulation layer, which is measured in a channel length direction, is substantially equal to a length of the second field insulation layer, which is measured in the channel length direction.

### Claim 12 (depends on 1)

The high voltage integrated device of claim 1, wherein a length of the second field insulation layer, which is measured in a channel length direction, is greater than a length of the first field insulation layer, which is measured in the channel length direction.

### Claim 13 (depends on 12)

The high voltage integrated device of claim 12, wherein the length of the second field insulation layer is at least 1.2 times longer than the length of the first field insulation layer.

### Claim 14 (depends on 1)

The high voltage integrated device of claim 1, wherein a thickness of the insulation layer is substantially equal to a thickness of the gate insulation layer.

### Claim 15 (depends on 14)

The high voltage integrated device of claim 14, wherein each of the first and second field insulation layers has a thickness greater than a thickness of the insulation layer.

### Claim 16 (depends on 15)

The high voltage integrated device of claim 15, wherein each of the first and second field insulation layers is at least thirty times thicker than the insulation layer.

### Claim 17 (depends on 1)

The high voltage integrated device of claim 1, wherein each of the first and second field insulation layers includes a high temperature oxide (HTO) layer.

### Claim 18 (depends on 1)

The high voltage integrated device of claim 1, wherein the gate insulation layer, the first field insulation layer, the insulation layer, and the second field insulation layer are arranged side by side at substantially the same level.