# US 9,520,491 B2 · Electrodes for semiconductor devices and methods of forming the same

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- Number: US 9,520,491 B2
- Document ID: US9520491B2
- Status: Granted
- Kind: B2
- Application number: 14/920,059
- Filed: 2015-10-22
- Published: 2016-02-11
- Granted: 2016-12-13
- Earliest claimed: 2013-02-15
- Assignees: Transphorm Inc.
- Applicants: Transphorm Inc.
- Inventors: Srabanti Chowdhury; Umesh Mishra; Yuvaraj Dora
- Web page: https://patentgrep.com/patent/US9520491B2

## CPC

- H10D 30/4755: {having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/47: having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D 62/405: {Orientations of crystalline planes}
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/0126: {the sectional shape being asymmetrical}
- H10D 64/01324: {characterised by the sectional shape, e.g. T or inverted-T}
- H10D 64/111: {Field plates}
- H10D 64/20: Electrodes characterised by their shapes, relative sizes or dispositions
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10D 64/411: {for FETs}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10P 14/40: of conductive or resistive materials
- H10W 20/082: {the openings being tapered via holes}
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10W 74/43: comprising oxides, nitrides or carbides, e.g. ceramics or glasses
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 64/0124: {to Group III-V semiconductors}
- H10D 64/0125: {characterised by the sectional shape, e.g. T or inverted T}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A III-N semiconductor HEMT device includes an electrode-defining layer on a III-N material structure. The electrode-defining layer has a recess with a first sidewall proximal to the drain and a second sidewall proximal to the source, each sidewall comprising a plurality of steps. A portion of the recess distal from the III-N material structure has a larger width than a portion of the recess proximal to the III-N material structure. An electrode is in the recess, the electrode including an extending portion over the first sidewall. A portion of the electrode-defining layer is between the extending portion and the III-N material structure. The first sidewall forms a first effective angle relative to the surface of the III-N material structure and the second sidewall forms a second effective angle relative to the surface of the III-N material structure, the second effective angle being larger than the first effective angle.

## Claims

### Claim 1

A III-N transistor, comprising:
a III-N material structure;
a source and a drain;
an electrode-defining layer having a thickness, the electrode-defining layer being over a surface of the III-N material structure, the electrode-defining layer having a recess with a first sidewall proximal to the drain and a second sidewall proximal to the source, the first and second sidewalls each comprising a plurality of steps; and
an electrode in the recess, the electrode including an extending portion at least partially over the first sidewall; wherein
the first sidewall forms a first effective angle relative to the surface of the III-N material structure and the second sidewall forms a second effective angle relative to the surface of the III-N material structure, the second effective angle being larger than the first effective angle;
the electrode includes a gate in a gate region of the transistor;
the plurality of steps in the first and second sidewalls each include a first step having a first step width directly adjacent to the gate, a second step having a second step width directly adjacent to the first step, and a third step having a third step width directly adjacent to the second step;
a ratio of the first step width to the second step width in the plurality of steps in the first sidewall is substantially the same as a ratio of the first step width to the second step width in the plurality of steps in the second sidewalk; and
a sum of the first step width, the second step width, and the third step width in the first sidewall is greater than a sum of the first step width, the second step width, and the third step width in the second sidewall.

### Claim 2 (depends on 1)

The transistor of claim 1, wherein the second effective angle is substantially larger than the first effective angle.

### Claim 3 (depends on 1)

The transistor of claim 1, wherein the second effective angle is at least 10 degrees larger than the first effective angle.

### Claim 4 (depends on 1)

The transistor of claim 1, wherein the III-N material structure comprises a first III-N material layer, a second III-N material layer, and a 2DEG channel induced in the first III-N material layer adjacent to the second III-N material layer as a result of a compositional difference between the first III-N material layer and the second III-N material layer.

### Claim 5 (depends on 4)

The transistor of claim 4, wherein the first III-N material layer includes GaN and the second III-N material layer includes AlGaN, AlInN, AlInGaN, or BAlInGaN.

### Claim 6 (depends on 4)

The transistor of claim 4, wherein the first III-N material layer and the second III-N material layer are group III-face or [0 0 0 1] oriented or group-III terminated semipolar layers, and the second III-N material layer is between the first III-N material layer and the electrode-defining layer.

### Claim 7 (depends on 4)

The transistor of claim 4, wherein the first III-N material layer and the second III-N material layer are N-face or [0 0 0 0−1] oriented or nitrogen-terminated semipolar layers, and the first III-N material layer is between the second III-N material layer and the electrode-defining layer.

### Claim 8 (depends on 4)

The transistor of claim 4, wherein the recess extends through the entire thickness of the electrode-defining layer.

### Claim 9 (depends on 8)

The transistor of claim 8, wherein the recess extends into the III-N material structure.

### Claim 10 (depends on 9)

The transistor of claim 9, wherein the recess extends through the 2DEG channel.

### Claim 11 (depends on 1)

The transistor of claim 1, wherein the electrode-defining layer comprises SiNx.

### Claim 12 (depends on 1)

The transistor of claim 1, wherein a thickness of the electrode-defining layer is between about 0.1 microns and 5 microns.

### Claim 13 (depends on 1)

The transistor of claim 1, further comprising a dielectric passivation layer between the III-N material structure and the electrode-defining layer, the dielectric passivation layer directly contacting a surface of the III-N material adjacent to the electrode.

### Claim 14 (depends on 13)

The transistor of claim 13, wherein the dielectric passivation layer comprises SiNx.

### Claim 15 (depends on 14)

The transistor of claim 14, wherein the dielectric passivation layer is between the electrode and the III-N material structure, such that the electrode does not directly contact the III-N material structure.

### Claim 16 (depends on 14)

The transistor of claim 14, further comprising an additional insulating layer between the dielectric passivation layer and the electrode-defining layer.

### Claim 17 (depends on 16)

The transistor of claim 16, wherein the additional insulating layer comprises AlN.

### Claim 18 (depends on 1)

The transistor of claim 1, wherein the extending portion of the electrode directly contacts the first sidewall.

### Claim 19 (depends on 1)

The transistor of claim 1, wherein a ratio of the first step width to the third step width in the plurality of steps in the first sidewall is substantially the same as a ratio of the first step width to the third step width in the plurality of steps in the second sidewall.

### Claim 20

A III-N transistor, comprising:
a III-N material structure;
an electrode-defining layer having a thickness, the electrode-defining layer being over a surface of the III-N material structure, the electrode-defining layer having a recess with a first sidewall proximal to a drain of the III-N transistor and a second sidewall opposite the first sidewall, the first and second sidewalls each comprising a plurality of steps; and
an electrode in the recess, the electrode including an extending portion at least partially over the first sidewall; wherein
the plurality of steps in the first and second sidewalls each include a first step having a first step width directly adjacent to the gate, a second step having a second step width directly adjacent to the first step, and a third step having a third step width directly adjacent to the second step; and
a sum of the first step width, the second step width, and the third step width in the first sidewall is greater than a sum of the first step width, the second step width, and the third step width in the second sidewall.

### Claim 21 (depends on 20)

The transistor of claim 20, wherein a ratio of the first step width to the second step width in the plurality of steps in the first sidewall is substantially the same as a ratio of the first step width to the second step width in the plurality of steps in the second sidewall.