# US 9,520,490 B2 · Semiconductor device and method of manufacturing the same

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- Number: US 9,520,490 B2
- Document ID: US9520490B2
- Status: Granted
- Kind: B2
- Application number: 14/320,037
- Filed: 2014-06-30
- Published: 2015-06-04
- Granted: 2016-12-13
- Earliest claimed: 2013-12-03
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Che-heung Kim
- Web page: https://patentgrep.com/patent/US9520490B2

## CPC

- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 62/8325: {Silicon carbide}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/111: {Field plates}
- H10D 84/01: Manufacture or treatment
- H10D 84/05: using Group III-V technology
- H10D 84/82: of only field-effect components
- H10D 89/10: Integrated device layouts
- H10D 30/471: {High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]}
- H10D 84/0126: {the components including insulated gates, e.g. IGFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device is a half bridged field effect transistor having a monolithic chip, and includes a semiconductor substrate with a 2-dimensional electron gas layer formed therein; a drain electrode formed on the semiconductor substrate; a first gate electrode, an output electrode, a second gate electrode, and a source electrode. The method of manufacturing the semiconductor device uses a method of monolithically forming a stack structure, which implements a half bridge function, on a substrate according to semiconductor processes.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate;
a first semiconductor layer on the substrate;
a second semiconductor layer on the first semiconductor layer, the second semiconductor layer inducing a 2-dimensional electron gas layer in the first semiconductor layer;
a first drain electrode, a first source electrode, and a first gate electrode on the second semiconductor layer and constituting a first transistor including the 2-dimensional electron gas layer;
a second drain electrode, a second source electrode, and a second gate electrode on the second semiconductor layer and constituting a second transistor including the 2-dimensional electron gas layer; and
an output electrode including the first source electrode and the second drain electrode.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first transistor, the output electrode, and the second transistor constitute a half-bridged field effect transistor (HBFET) cell.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the HBFET cell comprises a plurality of HBFET cells, and
wherein the plurality of HBFET cells are configured to implement an integrated HBFET.

### Claim 4 (depends on 2)

The semiconductor device of claim 2, wherein
the first drain electrode, the first gate electrode, the output electrode, the second gate electrode, and the second source electrode constitute a pentode unit, and
a plurality of pentode units are provided on the substrate.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, further comprising:
a first electrode pad configured to connect drain electrodes of a plurality of first transistors included in the plurality of pentode units to one another;
an output electrode pad configured to connect a plurality of output electrodes included in the plurality of pentode units to one another; and
a second electrode pad configured to connect source electrodes of a plurality of second transistors included in the plurality of pentode units to one another.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, further comprising an insulating layer substantially entirely covering the plurality of pentode units,
wherein the drain electrodes of the plurality of first transistors, the plurality of output electrodes, and the source electrodes of the plurality of second transistors are connected to the first electrode pad, the output electrode pad, and the second electrode pad, respectively, through contact holes penetrating the insulating layer.

### Claim 7

A semiconductor device comprising:
a semiconductor substrate with a 2-dimensional electron gas layer formed therein;
first and second gate electrodes on the semiconductor substrate, wherein the first gate electrode comprises a plurality of first gate lines spaced apart from one another, and the second gate electrode comprises a plurality of second gate lines interlocked with the plurality of first gate lines;
a plurality of first drain electrodes and first source electrodes, which constitute a plurality of first transistors having the plurality of first gate lines and the 2-dimensional electron gas layer;
a plurality of second drain electrodes and second source electrodes, which constitute a plurality of second transistors having the plurality of second gate lines and the 2-dimensional electron gas layer;
wherein the plurality of first drain electrodes and first source electrodes and the plurality of second drain electrodes and second source electrodes are disposed on a plurality of areas between the plurality of first and second gate lines.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, further comprising an output electrode including a source electrode of a first transistor and an adjacent drain electrode of a second transistor in the plurality of first transistors and the plurality of second transistors.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the plurality of first transistors, a plurality of output electrodes, and the plurality of second transistors constitute an integrated half bridge cell.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the first gate electrode further comprises a first connection portion configured to connect ends of the plurality of first gate lines to one another, and the second gate electrode further comprises a second connection portion configured to connect ends of the plurality of second gate lines to one another.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, further comprising:
a first electrode pad to which the first drain electrodes are connected;
an output electrode pad to which the plurality of output electrodes are connected; and
a second electrode pad to which the second source electrodes are connected.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, further comprising:
a first gate pad connected to the first connection portion; and
a second gate pad connected to the second connection portion.

### Claim 13 (depends on 7)

The semiconductor device of claim 7, further comprising:
a passivation layer substantially entirely covering the first gate electrode and the second gate electrode, and
a field plate extending from any one of a drain electrode, an output electrode, and a source electrode onto the passivation layer on an adjacent first gate line or adjacent second gate line.

### Claim 14 (depends on 7)

The semiconductor device of claim 7, wherein the semiconductor substrate comprises:
a substrate;
a first semiconductor layer on the substrate;
a second semiconductor layer on the first semiconductor layer, the second semiconductor layer inducing the 2-dimensional electron gas layer in the first semiconductor layer.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein the first semiconductor layer comprises at least one of GaN, InN, and GaAs; and
wherein the second semiconductor layer comprises at least one of AlGaN, AlInN, and AlGaAs.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, further comprising a buffer layer between the substrate and the first semiconductor layer.

### Claim 17 (depends on 1)

The semiconductor device of claim 1, wherein the first semiconductor layer comprises at least one of GaN, InN, and GaAs; and
wherein the second semiconductor layer comprises at least one of AlGaN, AlInN, and AlGaAs.

### Claim 18 (depends on 7)

The semiconductor device of claim 7, wherein at least two first gate lines are between the second gate lines.