# US 9,520,489 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,520,489 B2 - Document ID: US9520489B2 - Status: Granted - Kind: B2 - Application number: 14/604,796 - Filed: 2015-01-26 - Published: 2015-08-06 - Granted: 2016-12-13 - Earliest claimed: 2014-02-05 - Assignees: Renesas Electronics Corporation - Applicants: Renesas Electronics Corporation - Inventors: Tatsuo Nakayama; Hironobu Miyamoto; Yasuhiro Okamoto; Yoshinao Miura; Takashi Inoue - Web page: https://patentgrep.com/patent/US9520489B2 ## CPC - H10D 30/4732: {using Group III-V semiconductor material} - H10D 8/00: Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00) - H10D 62/115: {Dielectric isolations, e.g. air gaps} - H10D 62/8164: {comprising only semiconductor materials (potential variation in long-range structurally-disordered materials H10D62/8163)} - H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN} - H10D 64/257: {for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673)} - H10D 84/01: Manufacture or treatment - H10D 84/05: using Group III-V technology - H10D 88/00: Three-dimensional [3D] integrated devices - H10W 20/42: Vias, e.g. via plugs - H10D 62/343: {Gate regions of field-effect devices having PN junction gates} - H10D 62/357: {of FETs} - H10D 62/378: {Contact regions to the substrate regions} - H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)} - H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates} - H10D 84/0107: {Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs} - H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Characteristics of a semiconductor device are improved. The semiconductor device is configured to provide a trench that penetrates a barrier layer, and reaches a middle portion of a channel layer among an n+ layer, an n-type layer, a p-type layer, the channel layer, and the barrier layer which are formed above a substrate, a gate electrode arranged within the groove through a gate insulating film, and a source electrode and a drain electrode which are formed above the barrier layer on both sides of the gate electrode. The n-type layer and the drain electrode are electrically coupled to each other by a connection portion that reaches the n+ layer. The p-type layer and the source electrode are electrically coupled to each other by a connection portion that reaches the p-type layer. A diode including a p-type layer and an n-type layer is provided between the source electrode and the drain electrode, to thereby prevent the breaking of an element caused by an avalanche breakdown. ## Claims ### Claim 1 A semiconductor device, comprising: a first nitride semiconductor layer that is made over a substrate; a second nitride semiconductor layer that is formed on the first nitride semiconductor layer; a third nitride semiconductor layer that is formed on the second nitride semiconductor layer; a fourth nitride semiconductor layer that is formed on the third nitride semiconductor layer; a trench that penetrates through the fourth nitride semiconductor layer, and reaches a middle portion of the third nitride semiconductor layer; a gate electrode that is arranged within the trench through a gate insulating film; a first electrode and a second electrode that are formed above the fourth nitride semiconductor layer on both sides of the gate electrode; a first connection portion that connects the first electrode to the first nitride semiconductor layer; a second connection portion that connects the second electrode to the second nitride semiconductor layer; and an insulating film that is formed between the first connection portion and the second nitride semiconductor layer, wherein an electron affinity of the fourth nitride semiconductor layer is smaller than an electron affinity of the third nitride semiconductor layer, wherein the first nitride semiconductor layer contains impurities of a first conductivity type, wherein the second nitride semiconductor layer contains impurities of a second conductivity type that is a conductivity type opposite to the first conductivity type, wherein the substrate has a first region and a second region, wherein the gate electrode, the first electrode, and the second electrode are formed in the first region, wherein the second region is an device isolation region formed in the fourth nitride semiconductor layer and the third nitride semiconductor layer, wherein the first connection portion is arranged within a first through-hole that penetrates through the device isolation region and the second nitride semiconductor layer, and reaches the first nitride semiconductor layer, and wherein the insulating film is arranged between a side wall of the first through-hole and the first connection portion. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the second connection portion is arranged within a second through-hole that penetrates through the device isolation region, and reaches the second nitride semiconductor layer. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein a first terminal portion that is electrically coupled to the first electrode is arranged on the first connection portion. ### Claim 4 (depends on 3) The semiconductor device according to claim 3, wherein a second terminal portion that is electrically coupled to the second electrode is arranged on the second connection portion. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein a fifth nitride semiconductor layer is arranged under the first nitride semiconductor layer, and wherein the fifth nitride semiconductor layer contains the first conductivity type impurities higher in concentration than the first nitride semiconductor layer. ### Claim 6 (depends on 5) The semiconductor device according to claim 5, wherein the first connection portion is arranged within a first through-hole that penetrates through the device isolation region, the second nitride semiconductor layer, and the first nitride semiconductor layer, and reaches the fifth nitride semiconductor layer. ### Claim 7 (depends on 5) The semiconductor device according to claim 5, wherein a superlattice layer is arranged between the substrate and first nitride semiconductor layer, and wherein in the superlattice layer, two or more stacked bodies having a sixth nitride semiconductor layer, and a seventh nitride semiconductor layer different in electron affinity from the sixth nitride semiconductor layer are repetitively arranged. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, wherein the second connection portion is arranged within a second through-hole that penetrates through the fourth nitride semiconductor layer and the third nitride semiconductor layer, and reaches the second nitride semiconductor layer. ### Claim 9 (depends on 8) The semiconductor device according to claim 8, wherein the second electrode is arranged on the second connection portion. ### Claim 10 (depends on 1) The semiconductor device according to claim 1, wherein the first connection portion comprises a first conductive film, and the second connection portion comprises a second conductive film. ### Claim 11 (depends on 1) The semiconductor device according to claim 1, wherein the first connection portion comprises a first metal film, and the second connection portion comprises a second metal film. ### Claim 12 A semiconductor device, comprising: a first nitride semiconductor layer that is made over a substrate; a second nitride semiconductor layer that is formed on the first nitride semiconductor layer; a third nitride semiconductor layer that is formed on the second nitride semiconductor layer; a fourth nitride semiconductor layer that is formed on the third nitride semiconductor layer; a gate electrode that is arranged above the fourth nitride semiconductor layer through the fifth nitride semiconductor layer; a first electrode and a second electrode that are formed above the fourth nitride semiconductor layer on both sides of the gate electrode; a first connection portion that connects the first electrode to the first nitride semiconductor layer; a second connection portion that connects the second electrode to the second nitride semiconductor layer; and an insulating film that is formed between the first connection portion and the second nitride semiconductor layer, wherein an electron affinity of the fourth nitride semiconductor layer is smaller than an electron affinity of the third nitride semiconductor layer, wherein an electron affinity of the fifth nitride semiconductor layer is larger than an electron affinity of the fourth nitride semiconductor layer, wherein the first nitride semiconductor layer contains impurities of a first conductivity type, wherein the second nitride semiconductor layer contains impurities of a second conductivity type that is a conductivity type opposite to the first conductivity type, wherein the substrate has a first region and a second region, wherein the gate electrode, the first electrode, and the second electrode are formed in the first region, wherein the second region is a device isolation region formed in the fourth nitride semiconductor layer and the third nitride semiconductor layer, wherein the first connection portion is arranged within a first through-hole that penetrates through the device isolation region and the second nitride semiconductor layer, and reaches the first nitride semiconductor layer, wherein the insulating film is arranged between a side wall of the first through-hole and the first connection portion, and wherein the second connection portion is arranged within a second through-hole that penetrates through the device isolation region, and reaches the second nitride semiconductor layer. ### Claim 13 (depends on 12) The semiconductor device according to claim 12, wherein the second connection portion is arranged within the second through-hole that penetrates through the fourth nitride semiconductor layer and the third nitride semiconductor layer, and reaches the second nitride semiconductor layer. ### Claim 14 (depends on 13) The semiconductor device according to claim 13, wherein the second electrode is arranged on the second connection portion.