# US 9,520,484 B2 · Method for forming semiconductor nanowire transistors

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- Number: US 9,520,484 B2
- Document ID: US9520484B2
- Status: Granted
- Kind: B2
- Application number: 14/921,919
- Filed: 2015-10-23
- Published: 2016-04-28
- Granted: 2016-12-13
- Earliest claimed: 2014-10-24
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation
- Inventors: Zhongshan Hong
- Web page: https://patentgrep.com/patent/US9520484B2

## CPC

- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 12/031: {of IGBTs}
- H10D 62/119: {Nanowire, nanosheet or nanotube semiconductor bodies}
- H10D 62/8325: {Silicon carbide}
- H10P 50/242: {of Group IV materials}
- H10P 50/642: {Chemical etching}
- H10P 50/667: {by liquid etching only}
- H10P 50/71: {using masks for conductive or resistive materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method for forming a semiconductor device includes forming a semiconductor substrate having at least one fin structure on an insulator on a substrate. The fin structure includes a semiconductor layer overlying a sacrificial layer. The method also includes forming a patterned dummy gate on the substrate, forming a first spacer on both sides of the dummy gate, and using the dummy gate and the first spacer as a mask to remove a portion of the semiconductor layer and the sacrificial layer. Then the sacrificial layer is etched to form recessed regions on both sides of the sacrificial layer, and a second spacer is formed to cover both sides of the sacrificial layer and expose both sides of the semiconductor layer. The method also includes performing epitaxial growth on both sides of the semiconductor layer to form source and drain regions.

## Claims

### Claim 1

A method of forming a semiconductor nanowire device, the method comprising:
forming a semiconductor substrate having at least one fin structure on an insulator on a substrate, said fin structure including a semiconductor layer overlying a sacrificial layer;
forming a patterned dummy gate on the substrate;
forming a first spacer on both sides of the dummy gate;
using the dummy gate and the first spacer as a mask, removing a portion of the semiconductor layer and the sacrificial layer;
etching the sacrificial layer to form recessed regions on both sides of the sacrificial layer;
forming a second spacer to cover both sides of the sacrificial layer and exposing both sides of the semiconductor layer; and
performing epitaxial growth on both sides of the semiconductor layer to form source and drain regions.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming an interlayer dielectric around the source and the drain regions;
planarizing the interlayer dielectric to expose the dummy gate;
removing the dummy gate and the sacrificial layer; and
forming a high K dielectric layer and a metal gate surrounding the remaining semiconductor layer.

### Claim 3 (depends on 2)

The method of claim 2, wherein removing the dummy gate and the sacrificial layer comprises using isotropic dry etching to remove the dummy gate and the sacrificial layer.

### Claim 4 (depends on 2)

The method of claim 2, wherein removing the dummy gate and the sacrificial layer comprises:
using wet etching or dry etching to remove the dummy gate and a portion of the sacrificial layer; and
using isotropic etching to remove the remaining sacrificial layer.

### Claim 5 (depends on 4)

The method of claim 4, further comprising using hydrogen chloride gas at a temperature higher than 200° C. to remove the remaining sacrificial layer.

### Claim 6 (depends on 1)

The method of claim 1, further comprising: before forming the patterned dummy gate, forming a dummy insulator on the fin structure.

### Claim 7 (depends on 6)

The method of claim 6, wherein the dummy insulator comprises an oxide material or a nitride material.

### Claim 8 (depends on 1)

The method of claim 1, wherein forming the patterned dummy gate comprises:
forming a dummy gate material layer on the substrate overlying the insulator and the fin structure;
forming a patterned hard mask on the dummy gate material layer;
using the hard mask as a mask, etching the dummy gate material to form the patterned dummy gate.

### Claim 9 (depends on 8)

The method of claim 8, wherein the dummy gate comprises polysilicon or amorphous silicon.

### Claim 10 (depends on 8)

The method of claim 8, wherein the hard mask comprises SiN, SiCN, SiC, or SiON.

### Claim 11 (depends on 1)

The method of claim 1, wherein the lateral dimension of the sacrificial layer, after recessed regions are formed, is substantially the same as the lateral dimension of the dummy gate.

### Claim 12 (depends on 1)

The method of claim 1, further comprising removing the first spacer before forming the second spacer.

### Claim 13 (depends on 1)

The method of claim 1, wherein forming the fin structure comprises:
forming the sacrificial layer on the substrate;
forming the semiconductor layer on the sacrificial layer;
forming a patterned mask on the semiconductor layer; and
etching the semiconductor layer and the sacrificial layer to form the fin structure.

### Claim 14 (depends on 1)

The method of claim 1, wherein the sacrificial layer comprises Si, Ge, or SiGe, and the semiconductor layer comprises Si, SiGe, Ge, or a group III-V compound.

### Claim 15 (depends on 1)

The method of claim 1, wherein the source and drain regions comprise Si, SiGe, or SiC.

### Claim 16 (depends on 1)

The method of claim 1, wherein the first spacer comprises silicon oxide or amorphous carbon.