# US 9,520,483 B2 · Method for manufacturing semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,520,483 B2 - Document ID: US9520483B2 - Status: Granted - Kind: B2 - Application number: 14/994,927 - Filed: 2016-01-13 - Published: 2016-08-04 - Granted: 2016-12-13 - Earliest claimed: 2015-02-02 - Assignees: Semiconductor Manufacturing International (Shanghai) Corporation - Applicants: Semiconductor Manufacturing International (Shanghai) Corporation - Inventors: Xinpeng Wang - Web page: https://patentgrep.com/patent/US9520483B2 ## CPC - H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes} - H10D 64/0125: {characterised by the sectional shape, e.g. T or inverted T} - H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers} - H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers} - H10D 84/0135: {Manufacturing their gate conductors} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10P 14/40: of conductive or resistive materials - H10P 50/642: {Chemical etching} - H10P 50/694: {characterised by their behaviour during the process, e.g. soluble masks or redeposited masks} - H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling} - H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions - H10P 50/283: {by chemical means} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A method for manufacturing a semiconductor device may include forming a cavity between two insulating portions that are positioned on a semiconductor substrate. The cavity may include a first cavity portion and a second cavity portion. The second cavity portion may be positioned between the semiconductor substrate and the first cavity portion. A width of the second cavity portion may be less than a width of the first cavity portion. The method may further include providing a set of gate metal material through the first cavity portion into the second cavity portion for forming a metal gate member of the semiconductor device. ## Claims ### Claim 1 A method for manufacturing a semiconductor device, the method comprising: providing a dummy gate structure on a semiconductor substrate, wherein the dummy gate structure comprises a dummy gate member, an intermediate layer, and a mask layer, wherein the dummy gate member is positioned between the semiconductor substrate and the intermediate layer, and wherein the intermediate layer is positioned between the dummy gate member and the mask layer; providing an insulating structure, such that the dummy gate structure is positioned between two portions of the insulating structure; providing an etch-stop material layer that covers both the dummy gate structure and the insulating structure; providing a dielectric material layer that covers the etch-stop material layer; removing each of the mask layer, a portion of the etch-stop material layer that is positioned above the intermediate layer, and a portion of the dielectric material layer that is positioned above the intermediate layer; removing the intermediate layer or a remaining portion of the intermediate layer; partially removing a remaining portion of the insulating structure to form a first cavity portion; removing the dummy gate member to form a second cavity portion, wherein the second cavity portion is positioned between the semiconductor substrate and the first cavity portion, and wherein a width of the second cavity portion is less than a width of the first cavity portion; and providing a set of gate metal material through the first cavity portion into the second cavity portion for forming a metal gate member. ### Claim 2 (depends on 1) The method of claim 1, wherein a bottom portion of the first cavity portion is positioned between the semiconductor substrate and a top portion of the first cavity portion and is narrower than the top portion of the first cavity portion. ### Claim 3 (depends on 1) The method of claim 1, wherein a cross section of the first cavity portion has a trapezoid shape. ### Claim 4 (depends on 1) The method of claim 1, wherein a width of the metal gate member is equal to a width of a bottom portion of the first cavity portion. ### Claim 5 (depends on 1) The method of claim 1, wherein a thickness of the metal gate member is equal to a height of the second cavity portion. ### Claim 6 (depends on 1) The method of claim 1, wherein a thickness of the dummy gate member is equal to a thickness of the metal gate member. ### Claim 7 (depends on 1) The method of claim 1 comprising: configuring a thickness of the dummy gate member according to a predetermined thickness of the metal gate member. ### Claim 8 (depends on 1) The method of claim 1, wherein a height of the first cavity portion is less than or equal to a thickness of the intermediate layer. ### Claim 9 (depends on 1) The method of claim 1, wherein a height of the first cavity portion is equal to a thickness of the remaining portion of the intermediate layer. ### Claim 10 (depends on 1) The method of claim 1 comprising: controlling a height of the first cavity portion by partially removing the intermediate layer in a process step performed for removal of the mask layer, the portion of the etch-stop material layer, and the portion of the dielectric material layer. ### Claim 11 (depends on 1) The method of claim 1 comprising: configuring a thickness of the intermediate layer according to a predetermined height of the first cavity portion. ### Claim 12 (depends on 1) The method of claim 1, wherein the dummy gate member is formed of a polycrystalline silicon material, and wherein the intermediate layer is formed of a metal material. ### Claim 13 (depends on 1) The method of claim 1, wherein the mask layer comprises a silicon oxide layer and a silicon nitride layer, and wherein the silicon oxide layer is positioned between the intermediate layer and the silicon nitride layer. ### Claim 14 (depends on 1) The method of claim 1 comprising: performing a wet strip process for removing the dummy gate member, wherein a removal rate associated with a material of the dummy gate member is higher than a removal rate associated a material of the dielectric material layer. ### Claim 15 (depends on 1) The method of claim 1 comprising: etching the remaining portion of the insulating structure to form the first cavity portion and the two insulating portions, wherein the remaining portion of the insulating structure comprises two nitride members and two oxide members, wherein the two nitride members are positioned between the two oxide members, and wherein an etch rate associated with the nitride members is higher than an etch rate associated with the oxide members in the etching. ### Claim 16 (depends on 15) The method of claim 15, wherein the etch rate associated with the nitride members is greater than or equal to 30 times the etch rate associated with the oxide members in the etching. ### Claim 17 (depends on 15) The method of claim 15 comprising: using CHF3 and O2 in the etching. ### Claim 18 (depends on 15) The method of claim 15, wherein a depth of material removal associated with the etching is in a range of 10 angstroms to 100 angstroms. ### Claim 19 (depends on 1) The method of claim 1, wherein the two insulating portions include two nitride portions and two oxide portions, and wherein the two nitride portions are positioned between the two oxide portions and are shorter than the two oxide portions.