# US 9,520,477 B2 · Semiconductor device and fabricating method thereof

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- Number: US 9,520,477 B2
- Document ID: US9520477B2
- Status: Granted
- Kind: B2
- Application number: 14/658,505
- Filed: 2015-03-16
- Published: 2016-09-22
- Granted: 2016-12-13
- Earliest claimed: 2015-03-16
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: Chi-Cheng Hung; Yu-Sheng Wang; Kei-Wei Chen; Ying-Lang Wang
- Web page: https://patentgrep.com/patent/US9520477B2

## CPC

- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a substrate, a first and second source/drain regions, and a gate stack. The first and second source/drain regions are disposed on the substrate. The gate stack is disposed over the substrate to overlay a channel region between the first and second S/D regions. The gate stack includes a gate dielectric layer disposed over the substrate; and a metal alloy disposed on the gate dielectric layer and configured as a filling layer in the gate stack; wherein the metal alloy has a first corrosion resistance corresponding to an etchant designed for removing a carbon-containing polymer.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate;
a first and second source/drain regions on the substrate; and
a gate stack disposed over the substrate to overlay a channel region between the first and second S/D regions, the gate stack comprising:
a gate dielectric layer, disposed over the substrate;
a metal alloy, disposed on the gate dielectric layer and configured as a filling layer in the gate stack;
a work function layer, disposed over the gate dielectric layer;
a blocking layer, disposed over the work function layer; and
a wetting layer, disposed over the blocking layer;
wherein the metal alloy is disposed over the wetting layer, and the metal alloy has a first corrosion resistance corresponding to an etchant designed for removing a carbon-containing polymer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the metal alloy comprises a percentage of silicon at least about 0.2%.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the first corrosion resistance is higher than a second corrosion resistance of a metal alloy without the silicon.

### Claim 4 (depends on 2)

The semiconductor device of claim 2, wherein the metal alloy further comprises a percentage of copper at least about 0.5%.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the metal alloy comprises a first alloying component of silicon, a second alloying component of copper, and third alloying component of aluminum.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the gate dielectric layer surrounds the metal alloy.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the gate stack further comprises:
a capping layer, disposed between the gate dielectric layer and the work function layer.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the gate stack further comprises:
a non-conductive spacer, configured to be a side wall of the gate stack.

### Claim 9

A method for fabricating a semiconductor device, comprising:
providing a substrate;
forming a first and second source/drain (S/D) regions on the substrate; and
forming a gate stack over the substrate to overlay a channel region between the first and second S/D regions, comprising:
forming a gate dielectric layer over the substrate; and
forming a metal alloy on the gate dielectric layer to be a filling layer in the gate stack;
wherein the metal alloy has a first corrosion resistance corresponding to an etchant designed for removing a carbon-containing polymer, and forming the metal alloy includes sputtering an Al—Si—Cu target.

### Claim 10 (depends on 9)

The method of claim 9, further comprising forming a dielectric around the gate stack.

### Claim 11 (depends on 9)

The method of claim 9, further comprising forming a contact opening adjacent to the gate stack, wherein the contact opening exposes the first and second source/drain (S/D) regions.

### Claim 12 (depends on 11)

The method of claim 11, further comprising flowing the etchant into the contact opening to remove the carbon-containing polymer.

### Claim 13 (depends on 9)

The method of claim 9, wherein the first corrosion resistance is higher than a second corrosion resistance of a metal alloy without the silicon.

### Claim 14 (depends on 8)

The method of claim 8, further comprising:
forming a non-conductive spacer to be a side wall of the gate stack.

### Claim 15 (depends on 8)

The method of claim 8, wherein forming the gate stack over the substrate to overlay the channel region between the first and second S/D regions further comprises:
forming a work function layer over the gate dielectric layer;
forming a blocking layer over the work function layer; and
forming a wetting layer over the blocking layer;
wherein the metal alloy is disposed over the wetting layer.

### Claim 16 (depends on 15)

The method of claim 15, wherein forming the gate stack over the substrate to overlay the channel region between the first and second S/D regions further comprises:
forming a capping layer in between the gate dielectric layer and the work function layer.

### Claim 17 (depends on 9)

The method of claim 9, wherein the gate stack is formed in an interlayer dielectric layer (ILD) disposed on the substrate, and the method further comprises:
etching the ILD to form a contact opening to expose one of the first and second source/drain (S/D) regions by using the etchant.

### Claim 18 (depends on 17)

The method of claim 17, wherein the method further comprises:
forming a contact in the contact opening to couple to the one of the first and second source/drain (S/D) regions.

### Claim 19

A method for fabricating a semiconductor device, comprising:
providing a substrate;
forming a first and second source/drain (S/D) regions on the substrate; and
forming a gate stack over the substrate to overlay a channel region between the first and second S/D regions, comprising:
forming a gate dielectric layer over the substrate;
forming a metal alloy on the gate dielectric layer to be a filling layer in the gate stack;
forming a work function layer over the gate dielectric layer;
forming a blocking layer over the work function layer; and
forming a wetting layer over the blocking layer;
wherein the metal alloy is disposed over the wetting layer, and the metal alloy has a first corrosion resistance corresponding to an etchant designed for removing a carbon-containing polymer.