# US 9,520,475 B2 · Semiconductor device and method for producing the same

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- Number: US 9,520,475 B2
- Document ID: US9520475B2
- Status: Granted
- Kind: B2
- Application number: 14/301,914
- Filed: 2014-06-11
- Published: 2014-10-02
- Granted: 2016-12-13
- Earliest claimed: 2012-01-19
- Assignees: Fuji Electric Co., Ltd.
- Applicants: Fuji Electric Co., Ltd.
- Inventors: Masayuki Miyazaki; Takashi Yoshimura; Hiroshi Takishita; Hidenao Kuribayashi
- Web page: https://patentgrep.com/patent/US9520475B2

## CPC

- H10D 12/441: {Vertical IGBTs}
- H10D 8/00: Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00)
- H10D 8/01: Manufacture or treatment
- H10D 12/032: {of vertical IGBTs}
- H10D 62/105: {by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] (IGFETs having LDD or drain extension regions H10D30/601)}
- H10D 62/114: {PN junction isolations}
- H10D 62/133: {Emitter regions of BJTs}
- H10D 62/137: {Collector regions of BJTs}
- H10D 62/142: {Anode regions of thyristors or collector regions of gated bipolar-mode devices}
- H10D 62/177: {Base regions of bipolar transistors, e.g. BJTs or IGBTs}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 62/53: the imperfections being within the semiconductor body
- H10D 62/60: Impurity distributions or concentrations
- H10D 64/231: {Emitter or collector electrodes for bipolar transistors}
- H10D 64/66: Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/208: {of electrically inactive species}
- H10P 30/21: {of electrically active species}
- H10P 30/28: characterised by an annealing step, e.g. for activation of dopants
- H10P 34/42: with electromagnetic radiation, e.g. laser annealing (laser cutting H10P54/20)
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of producing a seminconductor device is disclosed in which, after proton implantation is performed, a hydrogen-induced donor is formed by a furnace annealing process to form an n-type field stop layer. A disorder generated in a proton passage region is reduced by a laser annealing process to form an n-type disorder reduction region. As such, the n-type field stop layer and the n-type disorder reduction region are formed by the proton implantation. Therefore, it is possible to provide a stable and inexpensive semiconductor device which has low conduction resistance and can improve electrical characteristics, such as a leakage current, and a method for producing the semiconductor device.

## Claims

### Claim 1

A semiconductor device comprising:
a p-type base layer that is provided in a surface layer of a first main surface of a semiconductor substrate, which is an n-type drift layer, and has a higher concentration than the drift layer:
an n-type emitter layer that is provided in the base layer and has a higher concentration than the base layer;
a gate insulating film that is provided so as to come into contact with the base layer, the emitter layer, and the drift layer;
a gate electrode that is provided on a surface of the gate insulating film so as to face the base layer, the emitter layer, and the drift layer;
an emitter electrode that is provided on the surfaces of the emitter layer and the base layer and is insulated from the gate electrode by an interlayer insulating film;
a p-type collector layer that is provided on a second main surface of the semiconductor substrate; and
at least one n-type intermediate layer that is provided between the drift layer and the collector layer and includes a pair of layers comprising (i) an n-type field stop layer with a higher concentration than the drift layer, positioned at a e of at least 15 μm from the second main surface of the semiconductor substrate, and (ii) an n-type disorder reduction region with a lower concentration than the field stop layer, which is adjacent to the collector layer side and is closer to the collector layer side than is the field stop layer.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the field stop layer includes a hydrogen-induced donor.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein carrier mobility in the disorder reduction region is lower than carrier mobility in the drift layer.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein a minimum value of the carrier mobility in the disorder reduction region is equal to or more than 20% of the carrier mobility in a crystal state.

### Claim 5 (depends on 4)

The semiconductor device according to claim 4, wherein a minimum value of the carrier mobility in the disorder reduction region is equal to or more than 50% of the carrier mobility in a crystal state.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein the doping concentration of the disorder reduction region is equal to or higher than the concentration of the drift layer.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, wherein the disorder reduction region includes a residual disorder which is introduced by hydrogen ion implantation.

### Claim 8 (depends on 7)

The semiconductor device according to claim 7, wherein the residual disorder is generated by reducing the disorder introduced by the hydrogen ion implantation using a heat treatment.

### Claim 9 (depends on 1)

The semiconductor device according to claim 1, wherein the depth of a position where carrier concentration is the maximum in the field stop layer which is adjacent to the base layer, with the drift layer interposed therebetween, from the second main surface is more than 15 μm.

### Claim 10 (depends on 1)

The semiconductor device according to claim 1, wherein a minimum value of the carrier mobility in the disorder reduction region is equal to or more than 20% of the carrier mobility in the drift layer.

### Claim 11 (depends on 1)

The semiconductor device according to claim 1, wherein a carrier concentration profile in the n-type field stop layer is a peak and a carrier concentration profile in the n-type disorder reduction region is a base of the peak.

### Claim 12

A semiconductor device comprising:
a p-type base layer that is provided in a surface layer of a first main surface of a semiconductor substrate, which is an n-type drift layer, and has a higher concentration than the drift layer;
an n-type emitter layer that is provided in the base layer and has a higher concentration than the base layer;
a gate insulating film that is provided so as to come into contact with the base layer, the emitter layer, and the drift layer;
a gate electrode that is provided on a surface of the gate insulating film so as to face the base layer, the emitter layer, and the drift layer;
an emitter electrode that is provided on the surfaces of the emitter layer and the base layer and is insulated from the gate electrode by an interlayer insulating film;
a p-type collector layer that is provided on a second main surface of the semiconductor substrate; and
at least one n-type intermediate layer that is provided between the drift layer and the collector layer and includes a pair of layers comprising (i) an n-type field stop layer with a higher concentration than the drift layer and (ii) an n-type disorder reduction region with a lower concentration than the field stop layer,
wherein, when q is an elementary charge, Nd is the average concentration of the drift layer, εs is the permittivity of the semiconductor substrate, Vrate is a rated voltage, JF is rated current density, and vsat is a saturated velocity in which a carrier speed is saturated with predetermined electric field intensity, a distance index L is represented by the following Expression (1):
L
=
ɛ
S
⁢
V
rate
q
⁡
(
J
F
qv
sat
+
N
d
)
Expression
⁢
⁢
(
1
)
and when the depth of the position where the carrier concentration is the maximum in the field stop layer which is adjacent to the base layer, with the drift layer interposed therebetween, from the second main surface is X and the thickness of the semiconductor substrate is W0, X=0−γL is established and γ is in the range of 0.2 to 1.5.

### Claim 13 (depends on 1)

The semiconductor device according to claim 1, wherein the field stop layer in the intermediate layer which comes into contact with the drift layer comes into contact with the drift layer, and the disorder reduction region in the intermediate layer which comes into contact with the collector layer comes into contact with the collector layer.

### Claim 14 (depends on 1)

The semiconductor device according to claim 1, wherein two or more intermediate layers are formed.

### Claim 15

A semiconductor device comprising:
a p-type anode layer that is provided in a surface layer of a first main surface of a semiconductor substrate, which is an n-type drift layer, and has a higher concentration than the drift layer;
an n-type cathode layer that is provided on a second main surface of the semiconductor substrate; and
at least one n-type intermediate layer that is provided between the drift layer and the collector layer and includes a pair of layers comprising (i) an n-type field stop layer with a higher concentration than the drift layer, positioned at a range of at least 15 μm from the second main surface of the semiconductor substrate and (ii) an n-type disorder reduction region with a lower concentration than the field stop layer, which is adjacent to the collector layer side and is closer to the collector layer than is the field stop layer.