# US 9,520,474 B2 · Methods of forming a semiconductor device with a gate stack having tapered sidewalls

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- Number: US 9,520,474 B2
- Document ID: US9520474B2
- Status: Granted
- Kind: B2
- Application number: 14/024,848
- Filed: 2013-09-12
- Published: 2015-03-12
- Granted: 2016-12-13
- Earliest claimed: 2013-09-12
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Limited
- Inventors: Che-Cheng Chang; Chang-Yin Chen; Yi-Jen Chen; Yung Jung Chang
- Web page: https://patentgrep.com/patent/US9520474B2

## CPC

- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/01324: {characterised by the sectional shape, e.g. T or inverted-T}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/681: {having a compositional variation, e.g. multilayered}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 84/0142: {the gate conductors having different shapes or dimensions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 14/416: {of highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers}
- H10P 50/266: {by vapour etching only}
- H10P 50/268: {of silicon-containing layers}
- H10P 50/283: {by chemical means}
- H10P 50/287: {by chemical means}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a metal gate stack. The metal gate stack includes a high-k gate dielectric and a metal gate electrode over the high-k gate dielectric. The metal gate electrode includes a first top surface and a second bottom surface substantially diametrically opposite the first top surface. The first top surface includes a first surface length and the second bottom surface includes a second surface length. The first surface length is larger than the second surface length. A method of forming a semiconductor device is provided.

## Claims

### Claim 1

A method of forming a semiconductor device, comprising:
forming a gate dielectric;
forming a silicon dummy layer over the gate dielectric;
performing a first etch using a first etch chemistry to etch through a first portion of the silicon dummy layer;
performing a second etch using a second etch chemistry to etch through a second portion of the silicon dummy layer, the second etch chemistry different than the first etch chemistry;
performing a third etch using a third etch chemistry to concurrently etch through a third portion of the silicon dummy layer and a portion of the gate dielectric to taper a sidewall of the gate dielectric and a sidewall of the silicon dummy layer such that a top surface length of a top surface of the silicon dummy layer is not equal to a bottom surface length of a bottom surface of the silicon dummy layer and a top surface length of a top surface of the gate dielectric is not equal to a bottom surface length of a bottom surface of the gate dielectric; and
replacing the silicon dummy layer with a metal gate electrode.

### Claim 2 (depends on 1)

The method of claim 1, comprising etching through a photoresist layer before forming the gate dielectric.

### Claim 3 (depends on 2)

The method of claim 2, comprising removing a BARC layer after etching through the photoresist layer.

### Claim 4 (depends on 3)

The method of claim 3, comprising removing a bottom layer after removing the BARC layer.

### Claim 5 (depends on 1)

The method of claim 1, wherein the second etch tapers a first portion of the sidewall of the silicon dummy layer and the third etch tapers a second portion of the sidewall of the silicon dummy layer.

### Claim 6 (depends on 1)

The method of claim 1, wherein the third etch is stopped when the sidewall of the gate dielectric and the sidewall of the silicon dummy layer lie in a same plane.

### Claim 7 (depends on 1)

The method of claim 1, comprising forming a cap layer over the gate dielectric before the forming a silicon dummy layer.

### Claim 8

A method of forming a semiconductor device, comprising:
performing a first etch process to etch through a first portion of a silicon dummy layer;
performing a second etch process to etch through a second portion of the silicon dummy layer, wherein the second etch process tapers a first portion of a sidewall of the silicon dummy layer; and
performing a third etch process to etch through a third portion of the silicon dummy layer, wherein:
the third etch process further etches a portion of a gate dielectric underlying the silicon dummy layer,
the third etch process tapers a second portion of the sidewall of the silicon dummy layer different than the first portion of the sidewall, and
the first portion of the sidewall and the second portion of the sidewall together define a tapered sidewall of the silicon dummy layer;
forming a sidewall spacer adjacent the tapered sidewall of the silicon dummy layer, wherein a sidewall of the sidewall spacer conforms to the tapered sidewall of the silicon dummy layer; and
replacing the silicon dummy layer with a metal gate electrode, wherein a sidewall of the metal gate electrode conforms to the sidewall of the sidewall spacer.

### Claim 9 (depends on 8)

The method of claim 8, the first etch process comprising a first flow rate of Cl2 and the second etch process comprising a second flow rate of Cl2 different than the first flow rate of Cl2.

### Claim 10 (depends on 8)

The method of claim 8, the first etch process comprising a first flow rate of CF4 and the second etch process comprising a second flow rate of CF4 different than the first flow rate of CF4.

### Claim 11 (depends on 10)

The method of claim 10, the third etch process comprising a third flow rate of CF4 different than the first flow rate of CF4 and different than the second flow rate of CF4.

### Claim 12 (depends on 8)

The method of claim 8, the third etch process comprising CHF3.

### Claim 13 (depends on 8)

The method of claim 8, wherein the portion of the gate dielectric comprises a sidewall of the gate dielectric and the third etch process tapers the sidewall of the gate dielectric to define a tapered sidewall of the gate dielectric.

### Claim 14 (depends on 13)

The method of claim 13, wherein the third etch process is stopped when the sidewall of the gate dielectric and the sidewall of the silicon dummy layer lie in a same plane.

### Claim 15 (depends on 8)

The method of claim 8, comprising:
forming a capping layer over the gate dielectric; and
forming the silicon dummy layer over the capping layer.

### Claim 16 (depends on 15)

The method of claim 15, wherein the third etch process further etches a portion of the capping layer.

### Claim 17

A method of forming a semiconductor device, comprising:
forming a gate dielectric;
forming a capping layer over the gate dielectric;
forming a silicon dummy layer over the capping layer;
performing a first etch process to etch through a first portion of the silicon dummy layer;
performing a second etch process to etch through a second portion of the silicon dummy layer, the second etch process different than the first etch process;
performing a third etch process to concurrently etch through a third portion of the silicon dummy layer and a portion of the capping layer to taper a sidewall of the capping layer and a sidewall of the silicon dummy layer; and
replacing the silicon dummy layer with a metal gate electrode.

### Claim 18 (depends on 17)

The method of claim 17, wherein the third etch process further etches a portion of the aate dielectric.

### Claim 19 (depends on 17)

The method of claim 17, the first etch process comprising a first flow rate of Cl2 and the second etch process comprising a second flow rate of Cl2 different than the first flow rate of Cl2.

### Claim 20 (depends on 17)

The method of claim 17, the first etch process comprising a first flow rate of CF4 and the second etch process comprising a second flow rate of CF4 different than the first flow rate of CF4.