# US 9,520,473 B2 · Method for producing semiconductor device and semiconductor device

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- Number: US 9,520,473 B2
- Document ID: US9520473B2
- Status: Granted
- Kind: B2
- Application number: 14/847,510
- Filed: 2015-09-08
- Published: 2015-12-31
- Granted: 2016-12-13
- Earliest claimed: 2013-08-07
- Assignees: Unisantis Electronics Singapore Pte. Ltd.
- Applicants: Unisantis Electronics Singapore Pte. Ltd.
- Inventors: Fujio Masuoka; Hiroki Nakamura
- Web page: https://patentgrep.com/patent/US9520473B2

## CPC

- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6728: {Vertical TFTs}
- H10D 30/674: {characterised by the active materials}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/512: {Disposition of the gate electrodes, e.g. buried gates}
- H10D 84/016: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/6736: {characterised by the shape of gate insulators}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method for producing a semiconductor device includes a first step of forming a first insulating film around a fin-shaped semiconductor layer; a second step of forming a first pillar-shaped semiconductor layer, a first dummy gate, a second pillar-shaped semiconductor layer, and a second dummy gate; a third step of forming a third dummy gate and a fourth dummy gate; a fourth step of forming a third diffusion layer in an upper portion of the fin-shaped semiconductor layer, in a lower portion of the first pillar-shaped semiconductor layer, and in a lower portion of the second pillar-shaped semiconductor layer; a fifth step of forming a gate electrode and a gate line around the first pillar-shaped semiconductor layer and forming a contact electrode and a contact line around the second pillar-shaped semiconductor layer; and a sixth step of forming first to fifth contacts.

## Claims

### Claim 1

A semiconductor device comprising:
a fin-shaped semiconductor layer on a semiconductor substrate;
a first insulating film around the fin-shaped semiconductor layer;
a second pillar-shaped semiconductor layer on the fin-shaped semiconductor layer;
a metal contact electrode around the second pillar-shaped semiconductor layer;
a metal contact line extending in a direction orthogonal to the fin-shaped semiconductor layer and connected to the metal contact electrode;
a third diffusion layer in an upper portion of the fin-shaped semiconductor layer and in a lower portion of the second pillar-shaped semiconductor layer, the contact electrode connected to the third diffusion layer;
a fourth contact surrounding an upper side wall of the second pillar-shaped semiconductor layer and connected to the contact electrode; and
a fifth contact connecting an upper portion of the fourth contact to an upper portion of the second pillar-shaped semiconductor layer.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, further comprising a first gate insulating film between the second pillar-shaped semiconductor layer and the contact electrode.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, further comprising a second gate insulating film between the upper side wall of the second pillar-shaped semiconductor layer and the fourth contact.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein a width of the second pillar-shaped semiconductor layer in a direction orthogonal to the fin-shaped semiconductor layer is the same as a width of the fin-shaped semiconductor layer in the direction orthogonal to the fin-shaped semiconductor layer.

### Claim 5 (depends on 2)

The semiconductor device according to claim 2, wherein the first gate insulating film extends around the contact electrode and the contact line.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein a width of the contact electrode in a direction orthogonal to the contact line is the same as a width of the contact line in the direction orthogonal to the contact line.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, wherein a width of the fourth contact in a direction orthogonal to the contact line is the same as a width of the contact electrode in the direction orthogonal to the contact line.

### Claim 8 (depends on 1)

The semiconductor device according to claim 1, wherein a width of the fifth contact in a direction orthogonal to the contact line is the same as a width of the fourth contact in the direction orthogonal to the contact line.

### Claim 9 (depends on 2)

The semiconductor device according to claim 2, further comprising:
a fin-shaped semiconductor layer on the semiconductor substrate;
a first insulating film around the fin-shaped semiconductor layer;
a first pillar-shaped semiconductor layer on the fin-shaped semiconductor layer,
wherein the first gate insulating film further extends around the first pillar-shaped semiconductor layer;
a metal gate electrode around the first gate insulating film;
a metal gate line extending in a direction orthogonal to the fin-shaped semiconductor layer connected to the gate electrode,
wherein the first gate insulating film further extends around and below the gate electrode and the gate line, the gate electrode having a width in a direction orthogonal to the gate line, the width being the same as a width of the gate line in the direction orthogonal to the gate line,
wherein the third diffusion layer is in an upper portion of the fin-shaped semiconductor layer and in a lower portion of the first pillar-shaped semiconductor layer,
the second gate insulating film extends around an upper side wall of the first pillar-shaped semiconductor layer;
a first contact of a second metal and around the second gate insulating film;
a second contact of a third metal and connecting an upper portion of the first contact to an upper portion of the first pillar-shaped semiconductor layer; and
a third contact of the second metal and the third metal on the gate line.

### Claim 10 (depends on 9)

The semiconductor device according to claim 9, wherein the second metal of the first contact has a work function of 4.0 eV to 4.2 eV.

### Claim 11 (depends on 9)

The semiconductor device according to claim 9, wherein the second metal of the first contact has a work function of 5.0 eV to 5.2 eV.