# US 9,520,471 B1 · Semiconductor device having gradient implant region and manufacturing method thereof

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 9,520,471 B1
- Document ID: US9520471B1
- Status: Granted
- Kind: B1
- Application number: 14/943,591
- Filed: 2015-11-17
- Granted: 2016-12-13
- Earliest claimed: 2015-11-17
- Assignees: Macronix International Co., Ltd.
- Applicants: Macronix International Co., Ltd
- Inventors: Ching-Lin Chan; Cheng-Chi Lin
- Web page: https://patentgrep.com/patent/US9520471B1

## CPC

- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 12/411: {Insulated-gate bipolar transistors [IGBT]}
- H10D 30/0281: {of lateral DMOS [LDMOS] FETs}
- H10D 30/0285: {using formation of insulating sidewall spacers}
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures}
- H10D 62/157: {Impurity concentrations or distributions}
- H10D 64/516: {the thicknesses being non-uniform}
- H10D 12/421: {on insulating layers or insulating substrates, e.g. thin-film IGBTs}
- H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/212: {Through-implantation}
- H10P 30/22: using masks
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a substrate having a first conductivity type, a high-voltage well having a second conductivity type and disposed in the substrate, a source well having the first conductivity type disposed in the high-voltage well, a drift region disposed in the high-voltage well and spaced apart from the source well, and a gradient implant region having the second conductivity type and disposed in the high-voltage well between the source well and the drift region.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate having a first conductivity type;
a high-voltage well having a second conductivity type and disposed in the substrate;
a source well having the first conductivity type disposed in the high-voltage well;
a drift region disposed in the high-voltage well and spaced apart from the source well; and
a gradient implant region having the second conductivity type and disposed in the high-voltage well between the source well and the drift region.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the gradient implant region includes:
a first portion disposed close to the drift region; and
a second portion disposed close to the source well,
a doping concentration of the first portion being higher than a doping concentration of the second portion.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein a depth of the first portion is greater than a depth of the second portion.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, further including:
a gate oxide layer disposed on the substrate between the source well and the drift region; and
a gate layer disposed on the gate oxide layer.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the gate oxide layer overlaps an edge portion of the source well.

### Claim 6 (depends on 4)

The semiconductor device of claim 4, further including an insulation layer having a portion disposed on the drift region,
the gradient implant region including a first portion disposed close to the drift region and a second portion disposed close to the source well,
the gate oxide layer being disposed adjacent to the portion of the insulation layer disposed on the drift region, and
the gate oxide laying overlapping the second portion of the gradient implant region.

### Claim 7 (depends on 4)

The semiconductor device of claim 4, wherein a width of the gate layer is greater than a width of the gradient implant region.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the gradient implant region overlaps an edge portion of the drift region.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the gradient implant region overlaps an edge portion of the source well.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, further including:
a second well disposed outside of the high-voltage well; and
a bulk region disposed in the second well.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, wherein the drift region includes a plurality of alternately arranged first sections and second sections,
each first section including a top region having the first conductivity type and a grade region having the second conductivity type disposed on the top region, and
each second section including the grade region.

### Claim 12 (depends on 1)

The semiconductor device of claim 1, wherein the semiconductor device is a metal oxide semiconductor (MOS) device,
the semiconductor device further including a drain region formed of a heavily doped region having the second conductivity type.

### Claim 13 (depends on 1)

The semiconductor device of claim 1, wherein the semiconductor device is an insulated gate bipolar transistor,
the semiconductor device further including a collector region formed of a heavily doped region having the first conductivity type.

### Claim 14

A method for manufacturing a semiconductor device, comprising:
providing a substrate having a first conductivity type;
forming a high-voltage well having a second conductivity type in the substrate;
forming a source well having the first conductivity type in the high-voltage well;
forming a drift region in the high-voltage well and spaced apart from the source well; and
forming a gradient implant region having the second conductivity type in the high-voltage well between the source well and the drift region.

### Claim 15 (depends on 14)

The method of claim 14, wherein the forming the gradient implant region includes:
forming a first portion disposed close to the drift region; and
forming a second portion disposed close to the source well,
a doping concentration of the first portion being higher than a doping concentration of the second portion.

### Claim 16 (depends on 15)

The method of claim 15, wherein the first portion is formed to have a greater depth than a depth of the second portion.

### Claim 17 (depends on 14)

The method of claim 14, wherein the forming the gradient implant region includes:
forming the gradient implant region to overlap an edge portion of drift region.

### Claim 18 (depends on 14)

The method of claim 14, wherein the forming the gradient implant region includes:
forming the gradient implant region to overlap an edge portion of the source well.

### Claim 19 (depends on 14)

The method of claim 14, wherein the drift region includes a plurality of alternately arranged first sections and second sections,
the forming a drift region in the high-voltage well including:
forming a top region having the first conductivity type in the first sections; and
forming a grade region having the second conductivity type in both of the first sections and the second sections.

### Claim 20 (depends on 14)

The method of claim 14, further including:
forming a gate oxide layer on the substrate between the source well and the drift region; and
forming a gate layer on the gate oxide layer.