# US 9,520,470 B1 · Lateral double diffused metal oxide semiconductor device and manufacturing method thereof

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- Number: US 9,520,470 B1
- Document ID: US9520470B1
- Status: Granted
- Kind: B1
- Application number: 14/939,913
- Filed: 2015-11-12
- Granted: 2016-12-13
- Earliest claimed: 2015-08-18
- Assignees: Richtek Technology Corporation
- Applicants: Richtek Technology Corporation
- Inventors: Tsung-Yi Huang
- Web page: https://patentgrep.com/patent/US9520470B1

## CPC

- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 30/0285: {using formation of insulating sidewall spacers}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/158: {Dispositions}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 62/60: Impurity distributions or concentrations
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/254: {for lateral devices wherein the source or drain electrodes extend entirely through the semiconductor bodies, e.g. via-holes for back side contacts}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10W 10/012: {using local oxidation of silicon [LOCOS]}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/13: formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A lateral double diffused metal oxide semiconductor device, includes: a P-type substrate, an epitaxial layer, a P-type high voltage well, a P-type body region, an N-type well, an isolation oxide region, a drift oxide region, a gate, an N-type contact region, a P-type contact region, a top source, a bottom source, and an N-type drain. The P-type body region is between and connects the P-type high voltage well and the surface of the epitaxial layer. The P-type body region includes a peak concentration region, which is beneath and indirect contact the surface of the epitaxial layer, wherein the peak concentration region has a highest P-type impurity concentration in the P-type body region. The P-type impurity concentration of the P-type body region is higher than a predetermined threshold to suppress a parasitic bipolar transistor such that it does not turn ON.

## Claims

### Claim 1

A lateral double diffused metal oxide semiconductor (LDMOS) device, comprising:
a P-type substrate, which has an upper surface and a lower surface opposite to each other in a vertical direction;
an epitaxial layer, which is formed on the P-type substrate and in direct contact with the upper surface, and has an epitaxial layer surface opposite to the upper surface in the vertical direction;
a P-type high voltage well, which is formed in the epitaxial layer, and is in direct contact with the upper surface of the P-type substrate;
a P-type body region, which is formed in the epitaxial layer and on the P-type high voltage well, the P-type body region being located between and connecting the P-type high voltage well and the epitaxial layer surface, wherein the P-type body region includes a peak concentration region which has a highest P-type impurity concentration in the P-type body region, the peak concentration region being in direct contact with and beneath the epitaxial layer surface;
an N-type well, which is formed in the epitaxial layer, the N-type well being in direct contact with and beneath the epitaxial layer surface in the vertical direction, and being adjacent to the P-type body region in a lateral direction;
an isolation oxide region, which is formed on the epitaxial layer to define an operation region;
a drift oxide region, which is formed in the operation region and on the epitaxial layer, the drift oxide region being in direct contact with the N-type well in the vertical direction;
a gate, which is formed in the operation region and on or above the epitaxial layer, the gate overlaying at least part of the drift oxide region, part of the N-type well and part of the P-type body region, part of the gate being in direct contact with the epitaxial layer;
an N-type contact region, which is formed in the P-type body region, and is in direct contact with and beneath the epitaxial layer surface in the vertical direction;
a P-type contact region, which is formed in the P-type body region, the P-type contact region being in direct contact with and beneath the epitaxial layer surface in the vertical direction, and being adjacent to the N-type contact region in the lateral direction;
an top source, which is formed on the epitaxial layer, and is in direct contact with the N-type contact region and the P-type contact region in the vertical direction;
a bottom source, which is formed beneath the lower surface of the P-type substrate in the vertical direction, and is in direct contact with the lower surface; and
an N-type drain, which is formed in the N-type well, and is in direct contact with and beneath the epitaxial layer surface, wherein the N-type drain is located between the drift oxide region and the isolation oxide region;
wherein part of the P-type body region is located beneath the N-type contact region and the P-type contact region in the vertical direction, wherein the peak concentration region is not located below the N-type contact region and the P-type contact region in the vertical direction, and the peak concentration region is adjacent to the N-type contact region in the lateral direction;
wherein a conductive current flows from the N-type drain to the bottom source in a normal operation when the LDMOS device is turned ON.

### Claim 2 (depends on 1)

The LDMOS device of claim 1, wherein the isolation oxide region is a local oxidation of silicon (LOCOS) structure or a shallow trench isolation (STI) structure, and the drift oxide region is a local oxidation of silicon (LOCOS) structure or a shallow trench isolation (STI) structure.

### Claim 3 (depends on 1)

The LDMOS device of claim 1, wherein the conductive current flows from the N-type drain, through the N-type well, the P-type body region, the N-type contact region, the top source, the P-type contact region, the P-type body region, the P-type high voltage well, and the P-type substrate, to the bottom source.

### Claim 4 (depends on 1)

The LDMOS device of claim 1, wherein the top source includes a metal layer or a metal silicide layer.

### Claim 5 (depends on 1)

The LDMOS device of claim 1, wherein the bottom source includes a metal layer or a metal silicide layer.