# US 9,520,469 B1 · Fabrication of fin structures having high germanium content

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- Number: US 9,520,469 B1
- Document ID: US9520469B1
- Status: Granted
- Kind: B1
- Application number: 14/854,665
- Filed: 2015-09-15
- Granted: 2016-12-13
- Earliest claimed: 2015-09-15
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Karthik Balakrishnan; Kangguo Cheng; Pouya Hashemi; Alexander Reznicek
- Web page: https://patentgrep.com/patent/US9520469B1

## CPC

- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 30/0245: {by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/751: {having composition variations in the channel regions}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/405: {Orientations of crystalline planes}
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10D 86/011: {comprising FinFETs}
- H10D 86/215: {comprising FinFETs}
- H10P 14/203: {using transformation of metal, e.g. oxidation or nitridation}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3466: {Crystal orientation}
- H10P 50/242: {of Group IV materials}
- H10P 50/283: {by chemical means}
- H10P 50/642: {Chemical etching}
- H10P 50/691: {for Group IV materials or Group III-V materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

High Ge content SiGe fins are provided, as well as improved techniques for forming high Ge content SiGe fins. A high Ge content fin is formed by obtaining one or more low Ge content SiGe fins having a hard mask deposited thereon; forming a high Ge content SiGe fin around the one or more low Ge content SiGe fins by oxidizing one or more sidewalls of the one or more low Ge content SiGe fins to create one or more oxide shells on the one or more sidewalls; removing the one or more oxide shells; and selectively removing the one or more low Ge content SiGe fins to produce a high Ge content SiGe fin device. A Fin Field Effect Transistor (FinFET) is also provided, comprising an insulating layer; and at least one high Ge content fin formed on the insulating layer, wherein the at least one high Ge content fin has asymmetric recesses into the insulator layer.

## Claims

### Claim 1

A method for forming one or more fins for a Fin Field Effect Transistor (FinFET), comprising:
obtaining one or more low Ge content SiGe fins having a hard mask deposited thereon;
forming a high Ge content SiGe fin around the one or more low Ge content SiGe fins by oxidizing one or more sidewalls of the one or more low Ge content SiGe fins to create one or more oxide shells on the one or more sidewalls;
removing the one or more oxide shells; and
selectively removing the one or more low Ge content SiGe fins to produce a high Ge content SiGe fin device having one or more high Ge content fins.

### Claim 2 (depends on 1)

The method of claim 1, wherein the step of removing the one or more oxide shells uses a Dilute Hydrofluoric Acid (DHF) dip.

### Claim 3 (depends on 1)

The method of claim 1, wherein the step of selectively removing the one or more low Ge content SiGe fins uses one or more of a wet etch process and a selective dry etch process.

### Claim 4 (depends on 1)

The method of claim 1, wherein the step of obtaining one or more low Ge content SiGe fins further comprises:
forming a SiGe layer on a semiconductor layer on an insulator;
forming a silicon dioxide layer on the SiGe layer;
selectively removing the silicon dioxide layer from the SiGe layer;
depositing and patterning the hard mask on the SiGe layer; and
etching the SiGe layer with the hard mask to expose the one or more low Ge content SiGe fins.

### Claim 5 (depends on 4)

The method of claim 4, wherein said silicon dioxide layer is formed on the SiGe layer a result of condensation.

### Claim 6 (depends on 4)

The method of claim 4, further comprising the step of selectively removing the hard mask using a hot phosphorous acid bath.

### Claim 7 (depends on 1)

The method of claim 1, wherein said one or more high Ge content fins have a Ge fraction equal to or greater than approximately 50%.

### Claim 8 (depends on 1)

The method of claim 1, further comprising the steps of:
depositing a sacrificial material between the one or more oxidized sidewalls; and
selectively removing the sacrificial material with the one or more low Ge content SiGe fins to produce the high Ge content SiGe fin device having one or more high Ge content fins.

### Claim 9 (depends on 8)

The method of claim 8, wherein the step of depositing said sacrificial material further comprises a chemical mechanical polishing (CMP).

### Claim 10 (depends on 1)

The method of claim 1, wherein the step of removing the one or more oxide shells removes a silicon dioxide layer on a SiGe layer into an insulator layer below a length of said one or more high Ge content fins.

### Claim 11 (depends on 10)

The method of claim 10, further comprising the step of selectively removing a sacrificial material deposited between the one or more oxidized sidewalls.

### Claim 12 (depends on 1)

The method of claim 1, further comprising the step of selectively removing the hard mask.

### Claim 13 (depends on 12)

The method of claim 12, wherein the step of removing the one or more oxide shells removes a silicon dioxide layer on a SiGe layer into an insulator layer below a length of said one or more high Ge content fins.

### Claim 14 (depends on 1)

The method of claim 1, wherein said one or more high Ge content fins are incorporated in an integrated circuit.

### Claim 15

A Fin Field Effect Transistor (FinFET), comprising:
an insulating layer; and
at least one high Ge content fin formed on said insulating layer, wherein said at least one high Ge content fin has asymmetric recesses into the insulator layer, wherein said asymmetric recesses comprise a first recess on a first side of said at least one high Ge content fin being deeper into the insulator layer than a second recess on a second side of said at least one high Ge content fin into the insulating layer.

### Claim 16 (depends on 15)

The FinFET of claim 15, wherein said one or more high Ge content fins have a Ge fraction equal to or greater than approximately 50%.

### Claim 17

An integrated circuit, comprising:
an insulating layer; and
at least one high Ge content fin formed on said insulating layer, wherein said at least one high Ge content fin has asymmetric recesses into the insulator layer, wherein said asymmetric recesses comprise a first recess on a first side of said at least one high Ge content fin being deeper into the insulator layer than a second recess on a second side of said at least one high Ge content fin into the insulating layer.

### Claim 18 (depends on 17)

The integrated circuit of claim 17, wherein said one or more high Ge content fins have a Ge fraction equal to or greater than approximately 50%.