# US 9,520,467 B1 · Field effect transistor structure and manufacturing method thereof

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- Number: US 9,520,467 B1
- Document ID: US9520467B1
- Status: Granted
- Kind: B1
- Application number: 14/840,752
- Filed: 2015-08-31
- Granted: 2016-12-13
- Earliest claimed: 2015-08-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: Fu-Yu Chu; Chih-Chang Cheng; Ruey-Hsin Liu
- Web page: https://patentgrep.com/patent/US9520467B1

## CPC

- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 62/307: {the doping variations being parallel to the channel lengths}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10P 30/21: {of electrically active species}
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure provides an FET structure including a substrate of a first conductive type having a top surface, a first gate over the top surface, a source and a drain of a second conductive type in the substrate, and a first channel under the first gate. A dopant concentration of a first conductive type includes double Gaussian peaks measured less than 200 nm beneath the top surface, from one end of the first gate to the other end of the first gate along the first channel. In some embodiments, the FET structure further including a second gate over the top surface and a second channel under the second gate. A dopant concentration of a first conductive type includes a single Gaussian peak measured less than 200 nm beneath the top surface, from one end of the second gate to the other end of the second gate along the second channel.

## Claims

### Claim 1

An FET structure, comprising:
a substrate of a first conductive type having a top surface;
a first gate over the top surface;
a source and a drain of a second conductive type in the substrate; and
a first channel under the first gate,
wherein a dopant concentration of a first conductive type comprises double Gaussian peaks measured less than 200 nm beneath the top surface, from one end of the first gate to the other end of the first gate along the first channel.

### Claim 2 (depends on 1)

The FET structure of claim 1, further comprising:
a second gate over the top surface; and
a second channel under the second gate;
wherein a dopant concentration of a first conductive type comprises a single Gaussian peak measured less than 200 nm beneath the top surface, from one end of the second gate to the other end of the second gate along the second channel.

### Claim 3 (depends on 1)

The FET structure of claim 1, wherein a length of the first gate is greater than a length of the second gate.

### Claim 4 (depends on 1)

The FET structure of claim 1, further comprising a single Gaussian peak of a dopant of the first conductive type at a t1 distance measured along a direction perpendicular to the first channel from the top surface into the substrate.

### Claim 5 (depends on 4)

The FET structure of claim 4, further comprising a t2 distance measured from a border of the source or drain to one of the double Gaussian peaks closer to the source of drain, respectively, wherein a ratio t1/t2 is in a range of from about 0.5 to about 1.5.

### Claim 6 (depends on 4)

The FET structure of claim 4, wherein a t1 distance is in a range of from about 0.01 μm to about 1 μm.

### Claim 7 (depends on 1)

The FET structure of claim 1, further comprising a lightly doped drain (LDD) region of the second conductive type under a sidewall spacer of the first gate.

### Claim 8 (depends on 1)

The FET structure of claim 1, wherein an average of the dopant concentration of the first conductive type measured less than 200 nm beneath the top surface, from one end of the first gate to the other end of the first gate along the first channel is less than an average of the dopant concentration of the first conductive type measured less than 200 nm beneath the top surface, from one end of the second gate to the other end of the second gate along the second channel.

### Claim 9

An analog FET structure, comprising:
a substrate of a first conductive type having a top surface;
a shorter gate over the top surface;
a source and a drain of a second conductive type in the substrate; and
a shorter channel under the shorter gate,
wherein a dopant concentration of a first conductive type comprises a single Gaussian peak measured less than 200 nm beneath the top surface, from one end of the shorter gate to the other end of the shorter gate along the shorter channel.

### Claim 10 (depends on 9)

The analog FET structure of claim 9, further comprising:
a longer gate over the top surface; and
a longer channel under the longer gate;
wherein a dopant concentration of a first conductive type comprises double Gaussian peaks measured less than 200 nm beneath the top surface, from one end of the longer gate to the other end of the longer gate along the longer channel.

### Claim 11 (depends on 9)

The analog FET structure of claim 9, wherein the single Gaussian peak of the dopant concentration of the first conductive type is approximately 1E17/cm3.

### Claim 12 (depends on 10)

The analog FET structure of claim 10, wherein a local minimum between the double Gaussian peaks of the dopant concentration of the first conductive type is approximately from 1E13/cm3 to about 1E16/cm3.

### Claim 13 (depends on 9)

The analog FET structure of claim 9, wherein a border of the source or drain to the single Gaussian peak comprises a t2 distance along the shorter channel, the t2 distance is shorter than one half of a length of the shorter gate.

### Claim 14 (depends on 9)

The analog FET structure of claim 9, further comprising a single Gaussian peak of a dopant of the first conductive type at a t1 distance measured along a direction perpendicular to the shorter channel from the top surface into the substrate, wherein a ratio t1/t2 is in a range of from about 0.5 to about 1.5.

### Claim 15 (depends on 10)

The analog FET structure of claim 10, wherein an average of the dopant concentration of the first conductive type measured less than 200 nm beneath the top surface, from one end of the shorter gate to the other end of the shorter gate along the shorter channel is one to four order greater than an average of the dopant concentration of the first conductive type measured less than 200 nm beneath the top surface, from one end of the longer gate to the other end of the longer gate along the longer channel.

### Claim 16

A method for manufacturing an FET structure, comprising:
forming a gate on a top surface of a substrate of a first conductive type;
performing a channel implant at a tilting angle approximately from 30 degrees to 45 degrees so as to form a dopant concentration profile of the first conductive type having at least a single Gaussian peak measured less than 200 nm beneath the top surface, from one end of the gate to the other end of the gate along a channel under the gate;
forming a sidewall spacer of the gate; and
performing a source and a drain implant.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
performing an LDD implant at a zero tilting angle.

### Claim 18 (depends on 16)

The method of claim 16, wherein the performing the channel implant at the tilting angle approximately from 30 degrees to 45 degrees comprises applying an implant energy of from about 10 KeV to about 120 KeV.

### Claim 19 (depends on 16)

The method of claim 16, wherein the performing the channel implant at the tilting angle approximately from 30 degrees to 45 degrees comprises applying more than one implant operation at different implant energies.

### Claim 20 (depends on 16)

The method of claim 16, further comprising applying an isolation implant prior to the channel implant so as to form a uniform dopant concentration profile of the first conductive type measured below the dopant concentration profile of the channel implant from one end of the gate to the other end of the gate along a direction of the channel.