# US 9,520,463 B2 · Super junction semiconductor device including edge termination

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- Number: US 9,520,463 B2
- Document ID: US9520463B2
- Status: Granted
- Kind: B2
- Application number: 14/795,322
- Filed: 2015-07-09
- Published: 2015-10-29
- Granted: 2016-12-13
- Earliest claimed: 2013-07-31
- Assignees: Infineon Technologies Austra AG
- Applicants: Infineon Technologies Austria AG
- Inventors: Hans Weber
- Web page: https://patentgrep.com/patent/US9520463B2

## CPC

- H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/665: {having edge termination structures}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/058: {by using trenches, e.g. implanting into sidewalls of trenches or refilling trenches}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 64/111: {Field plates}
- H10P 50/613: {of Group IV materials}
- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 62/112: {for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A super junction semiconductor device includes a super junction structure and a channel stopper structure. The super junction structure includes first and second areas alternately arranged along a first lateral direction and extending in parallel along a second lateral direction. Each one of the first areas includes a first semiconductor region of a first conductivity type. Each one of the second areas includes, along the first lateral direction, an inner area between opposite second semiconductor regions of a second conductivity type opposite to the first conductivity type. The channel stopper structure includes a doped semiconductor region electrically coupled to a field plate. The second semiconductor regions extend along the second lateral direction from the transistor cell area through the edge termination area overlap with the field plate.

## Claims

### Claim 1

A super junction semiconductor device, comprising:
a super junction structure including first and second areas alternately arranged along a first lateral direction and extending in parallel along a second lateral direction;
each one of the first areas includes a first semiconductor region of a first conductivity type; each one of the second areas includes, along the first lateral direction, an inner area between opposite second semiconductor regions of a second conductivity type opposite to the first conductivity type; and
a channel stopper structure including a doped semiconductor region electrically coupled to a field plate, wherein the opposite second semiconductor regions extending along the second lateral direction from the transistor cell area through the edge termination area overlap with the field plate, and merge by enclosing the inner area.

### Claim 2 (depends on 1)

The super junction semiconductor device of claim 1, wherein the doped semiconductor region is at a first chip side and electrically couples an electrode at a second chip side opposite to the first chip side to the field plate at the first chip side.

### Claim 3 (depends on 1)

The super junction semiconductor device of claim 1, wherein a width w1 of the first of the first semiconductor region in a transistor cell area is greater than in an edge termination area, and a width w2 of each one of the second semiconductor regions in the transistor cell area is greater than in the edge termination area.

### Claim 4 (depends on 1)

The super junction semiconductor device of claim 1, further comprising a transition area between the transistor cell area and the edge termination area, wherein the widths w1, w2 continuously change, along the second lateral direction, from a first value in the transistor cell area to a second value in the edge termination area, respectively.

### Claim 5 (depends on 1)

The super junction semiconductor device of claim 1, further comprising a transition area between the transistor cell area and the edge termination area, wherein the widths w1, w2 in different ones of the alternately arranged first and second areas gradually change, along the first lateral direction, from a first value in the transistor cell area to a second value in the edge termination area, respectively.

### Claim 6 (depends on 1)

The super junction semiconductor device of claim 1, further comprising a transition area between the transistor cell area and the edge termination area, wherein a depth d2 of the second semiconductor regions in different ones of the second areas decreases, along the first lateral direction, from the transistor cell area into the transition area.