# US 9,520,462 B1 · Semiconductor device having capacitor integrated therein > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,520,462 B1 - Document ID: US9520462B1 - Status: Granted - Kind: B1 - Application number: 14/948,942 - Filed: 2015-11-23 - Granted: 2016-12-13 - Earliest claimed: 2012-01-06 - Assignees: Maxim Integrated Products, Inc. - Applicants: Maxim Integrated Products, Inc. - Inventors: Khanh Tran; Joseph P. Ellul; Anuranjan Srivastava; Kiyoko Ikeuchi; Scott W. Barry - Web page: https://patentgrep.com/patent/US9520462B1 ## CPC - H10D 1/042: {using deposition processes to form electrode extensions} - H10D 1/665: {Trench conductor-insulator-semiconductor capacitors, e.g. trench MOS capacitors} - H10D 1/68: Capacitors having no potential barriers - H10D 1/716: {having vertical extensions} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract Semiconductor devices are described that include a capacitor integrated therein. In an implementation, the semiconductor devices include a substrate including a dopant material of a first conductivity type. A plurality of trenches are formed within the substrate. The semiconductor devices also include a diffusion region having dopant material of a second conductivity type formed proximate to the trenches. A capacitor is formed within the trenches and at least partially over the substrate. The capacitor includes at least a first electrode, a second electrode, and a dielectric material formed between the first and second electrodes. ## Claims ### Claim 1 A semiconductor device comprising: a substrate having dopant material of a first conductivity type; a plurality of trenches disposed within the substrate; a diffusion region disposed proximate to the plurality of trenches, the diffusion region having dopant material of a second conductivity type; and a metal-insulator-metal (MIM) capacitor formed within each trench of the plurality of trenches wherein the plurality of trenches have an aspect ratio ranging from about one hundred and twenty-five to one (125:1) to about one hundred and fifty to one (150:1) such that the metal-insulator-metal capacitor comprises a capacitive density ranging from three hundred femtoFarads per square micrometer (300 fF/um2) to two thousand femtoFarads per square micrometer (2,000 fF/um2). ### Claim 2 (depends on 1) The semiconductor device as recited in claim 1, wherein the metal-insulator-metal capacitor includes a seam for facilitating stress management. ### Claim 3 (depends on 1) The semiconductor device as recited in claim 1, wherein the metal-insulator-metal capacitor includes a low-stress conductive layer to fill and seal the plurality of trenches after formation of the metal-insulator-metal capacitor. ### Claim 4 (depends on 1) The semiconductor device as recited in claim 1, wherein the metal-insulator-metal capacitor includes a first electrode, a second electrode, and a dielectric layer disposed between the first electrode and the second electrode. ### Claim 5 (depends on 4) The semiconductor device as recited in claim 4, wherein at least one of the first electrode or the second electrode is titanium-nitride. ### Claim 6 (depends on 4) The semiconductor device as recited in claim 4, wherein the dielectric layer is a high-k material. ### Claim 7 (depends on 1) The semiconductor device as recited in claim 1, wherein the diffusion region is self-aligned to the plurality of trenches. ### Claim 8 (depends on 1) The semiconductor device as recited in claim 1, wherein the regions between capacitors are doped with higher but same-polarity dopant type as the substrate. ### Claim 9 A method comprising: forming a plurality of trenches within a semiconductor wafer, the semiconductor wafer including dopant material of a first conductivity type; forming a diffusion region proximate to the plurality of trenches, the diffusion region including dopant material of a second conductivity type; and forming a metal-insulator-metal (MIM) capacitor within each trench of the plurality of trenches and at least partially over the semiconductor wafer, wherein the plurality of trenches have an aspect ratio ranging from about one hundred and twenty-five to one (125:1) to about one hundred and fifty to one (150:1) such that the metal-insulator-metal capacitor comprises a capacitive density ranging from three hundred femtoFarads per square micrometer (300 fF/um2) to two thousand femtoFarads per square micrometer (2,000 fF/um2). ### Claim 10 (depends on 9) The method as recited in claim 9, wherein the metal-insulator-metal capacitor includes a seam for facilitating stress management. ### Claim 11 (depends on 9) The method as recited in claim 9, wherein the metal-insulator-metal capacitor includes a low-stress conductive layer to fill and seal the trenches after formation of the capacitor. ### Claim 12 (depends on 9) The method as recited in claim 9, wherein forming a metal-insulator-metal (MIM) capacitor further comprises forming a first electrode within each trench of the plurality of trenches and at least partially over the semiconductor wafer; forming a dielectric layer at least partially over the first electrode; and forming a second electrode at least partially over the dielectric layer. ### Claim 13 (depends on 9) The method as recited in claim 9, wherein the diffusion region is self-aligned to the plurality of trenches. ### Claim 14 (depends on 9) The method as recited in claim 9, wherein the regions between capacitors are doped with higher but same-polarity dopant type as the substrate. ### Claim 15 A semiconductor device comprising: a substrate having dopant material of a first conductivity type; a plurality of trenches disposed within the substrate; a diffusion region disposed proximate to the plurality of trenches, the diffusion region having dopant material of a second conductivity type; and a dual metal-insulator-metal (MIM) capacitor formed within each trench of the plurality of trenches, wherein the plurality of trenches have an aspect ratio ranging from about one hundred and twenty-five to one (125:1) to about one hundred and fifty to one (150:1) such that the metal-insulator-metal capacitor comprises a capacitive density ranging from three hundred femtoFarads per square micrometer (300 fF/um2) to two thousand femtoFarads per square micrometer (2,000 fF/um2). ### Claim 16 (depends on 15) The semiconductor device as recited in claim 15, wherein an etch-stop layer is disposed over the second electrode. ### Claim 17 (depends on 16) The semiconductor device as recited in claim 16, wherein the etch-stop layer is at least one of silicon-nitride or silicon oxynitride. ### Claim 18 (depends on 15) The semiconductor device as recited in claim 15, wherein the second electrode is thickened by an alternating composition of titanium-nitride-doped polysilicon-titanium-nitride.