# US 9,520,448 B1 · Compact ReRAM based PFGA

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- Number: US 9,520,448 B1
- Document ID: US9520448B1
- Status: Granted
- Kind: B1
- Application number: 15/233,054
- Filed: 2016-08-10
- Published: 2016-12-01
- Granted: 2016-12-13
- Earliest claimed: 2015-03-12
- Assignees: Microsemi SoC Corporation
- Applicants: Microsemi SoC Corporation
- Inventors: John L. McCollum; Fethi Dhaoui
- Web page: https://patentgrep.com/patent/US9520448B1

## CPC

- H10B 63/34: {of the vertical channel field-effect transistor type}
- G11C 13/003: {Cell access}
- H03K 19/1776: for memories
- H10N 70/011: {Manufacture or treatment of multistable switching devices}
- H10W 20/01: {Manufacture or treatment}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 2213/74: Array wherein each memory cell has more than one access device
- G11C 2213/78: Array wherein the memory cells of a group share an access device, all the memory cells of the group having a common electrode and the access device being not part of a word line or a bit line driver
- G11C 2213/79: Array wherein the access device being a transistor
- G11C 2213/82: Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A push-pull resistive random access memory cell circuit includes an output node, a word line, a first bit line, and a second bit line. A first resistive random access memory device is connected between the first bit line and the output node and a second resistive random access memory device is connected between the output node and the second bit line. A first programming transistor has a gate connected to the word line, a drain connected to the output node, and a source. A second programming transistor has a gate connected to the word line, a drain connected to the source of the first programming transistor, and a source. The first and second programming transistors have the same pitch, the same channel length, and the same gate dielectric thickness, the gate dielectric thickness chosen to withstand programming and erase potentials encountered during operation of the push-pull ReRAM cell circuit.

## Claims

### Claim 1

A method for fabricating a push-pull resistive random access memory cell circuit comprising:
the output node and the second bit line;
forming source and drain regions for first and second programming transistors in a semiconductor substrate, the drain region for the second programming transistor connected to the source of the first programming transistor, the source and drain regions for first and second programming transistors formed such that the first and second programming transistors have an equal pitch and an equal channel length;
forming gate dielectric regions over the source and drain regions for first and second programming transistors, the gate dielectric regions having equal thicknesses chosen to withstand programming and erase potentials encountered during operation of the push-pull ReRAM cell circuit;
forming gate regions for the first and second programming transistors over the gate dielectric regions;
forming a first dielectric region over the gates of the first and second programming transistors;
forming in the first dielectric region a drain contact to the drain of the first programming transistor, a source contact to the source of the second programming transistor, and gate contacts to the gates of the first and second programming transistors;
forming an output node, a word line source, and a word line for the memory cell circuit in a first metal interconnect layer, the output node connected to the drain contact, the word line source connected to the source contact, and the word line connected to the gate contacts of the first and second programming transistors;
forming first and second resistive random access memory devices each having first and second terminals, the first terminal of each of the first and second resistive random access memory devices connected to the output node;
forming a second dielectric region over the second terminals of the first and second resistive random access memory devices;
forming in the second dielectric region a first bit line contact to the second terminal of the first resistive random access memory device and a second bit line contact to the second terminal of the second resistive random access memory device; and
forming first and second bit lines in a second metal interconnect layer, the first bit line connected to the first bit line contact and the second bit line connected to the second bit line contact.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming in the semiconductor substrate source and drain regions for input/output transistors at the same time as forming the source and drain regions for the first and second programming transistors; and
forming gate dielectric regions over the source and drain regions of the input/output transistors at the same time as forming the gate dielectric regions over the first and second programming transistors, the gate dielectric regions of the input/output transistors being equal to the thickness of the gate dielectric of the first and second programming transistors.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
forming in the semiconductor substrate source and drain regions for at least one switch transistor in the push-pull resistive random access memory cell circuit at the same time as forming the source and drain regions for the first and second programming transistors, the source and drain regions for the at least one switch transistor formed such that the at least one switch transistor has a pitch and a channel length equal to the pitch and channel length, respectively, of the first and second programming transistors;
forming a gate dielectric region over the source and drain regions of the at least one switch transistor at the same time as forming the gate dielectric regions over the first and second programming transistors, the gate dielectric region of the at least one switch transistor having a thickness equal to the thickness of the gate dielectric of the first and second programming transistors; and
forming in the first dielectric region at the same time as forming the drain contact, the source contact, and the gate contacts, a switch gate contact to the gate of the at least one switch transistor.

### Claim 4 (depends on 1)

The method of claim 1 further comprising:
forming in the semiconductor substrate source and drain regions for logic transistors at the same time as forming the source and drain regions for the first and second programming transistors;
forming gate dielectric regions over the source and drain regions for logic transistors, the gate dielectric regions for the logic transistors having thicknesses less than the thickness of the gate dielectric of the first and second programming transistors.

### Claim 5 (depends on 1)

The method of claim 1 wherein forming source and drain regions for first and second programming transistors in a semiconductor substrate comprises forming a single region to serve as both the source of the first programming transistor and the drain of the second programming transistor.

### Claim 6 (depends on 1)

The method of claim 1 wherein forming source and drain regions for first and second programming transistors in the semiconductor substrate comprises forming n-type regions in a p-type substrate.

### Claim 7 (depends on 6)

The method of claim 6 wherein forming n-type regions in a p-type substrate comprises forming n-type regions in a p-type well.

### Claim 8

A method for fabricating a push-pull resistive random access memory cell circuit for an integrated circuit on a semiconductor substrate, the method comprising:
forming active regions for first and second programming transistors and for at least one switch transistor in the semiconductor substrate and forming source and drain regions in the active regions for first and second programming transistors defining channels for the first and second programming transistors such that the first and second programming transistors have a pitch length and a channel length respectively equal to the pitch length and channel length of logic transistors formed in the integrated circuit;
forming source and drain regions defining a channel for the at least one switch transistor in the active region for at least one switch transistor;
forming gates for the first and second programming transistors over the channels for the first and second programming transistors, the gates for the first and second programming transistors both having a same thickness;
forming a gate for the at least one switch transistor over the channel for the at least one switch transistor;
forming contacts to each of the source and gate of the first programming transistor, to the drain and gate of the second programming transistor, and to the gate of the at least one switch transistor;
forming from a first segment of a first level metal interconnect line a source word line for the push-pull resistive random access memory cell circuit, the first segment of the first metal interconnect line connected to the contact to the source of the first programming transistor;
forming from a second segment of the first level metal interconnect line a word line for the push-pull resistive random access memory cell circuit, the second segment of the first metal interconnect line connected to the contacts to the gates of the first and second programming transistors;
forming from a third segment of the first level metal interconnect line an interconnect conductor connected to the contacts to the drain of the second programming transistor and the gate of the at least one switch transistor;
forming a fourth segment of the first level metal interconnect line;
forming a first resistive random access memory device over the third segment of the first level metal interconnect line;
forming a second resistive random access memory device over the fourth segment of the first level metal interconnect line;
forming contacts to each of the first and second resistive random access memory devices, to the third segment of the first metal interconnect layer, and to the fourth segment of the first level metal interconnect line;
forming from a first segment of a second level metal interconnect line a bit line for the push-pull resistive random access memory cell circuit connected to the contact to the second resistive random access memory device;
forming from a second segment of the second level metal interconnect line a complementary bit line for the push-pull resistive random access memory cell circuit connected to the contact to the first resistive random access memory device; and
forming a third segment of the second level metal interconnect line connected to the contacts to the third segment of the first metal interconnect layer and the first resistive random access memory device.

### Claim 9 (depends on 8)

The method of claim 8 wherein forming source and drain regions in the active regions for first and second programming transistors comprises forming a single region to serve as both the drain of the first programming transistor and the source of the second programming transistor.