# US 9,520,447 B2 · Memory cells having a common gate terminal

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- Number: US 9,520,447 B2
- Document ID: US9520447B2
- Status: Granted
- Kind: B2
- Application number: 14/740,738
- Filed: 2015-06-16
- Published: 2015-10-29
- Granted: 2016-12-13
- Earliest claimed: 2012-01-13
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Rajesh N. Gupta; Farid Nemati
- Web page: https://patentgrep.com/patent/US9520447B2

## CPC

- H10B 63/34: {of the vertical channel field-effect transistor type}
- G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell}
- G11C 11/1659: {Cell access}
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10N 70/011: {Manufacture or treatment of multistable switching devices}
- H10N 70/021: {Formation of switching materials, e.g. deposition of layers}
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/882: {Compounds of sulfur, selenium or tellurium, e.g. chalcogenides}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10N 70/8836: {Complex metal oxides, e.g. perovskites, spinels}
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

Arrays of memory cells having a common gate terminal and methods of operating and forming the same are described herein. As an example, an array of memory cells may include a group of memory cells each having a resistive storage element coupled to a select device. Each select device includes a first terminal, a second terminal, and a gate terminal, where the gate terminal is common to each memory cell of the group.

## Claims

### Claim 1

A method of forming an array of memory cells, the method comprising:
forming a first metal material on a substrate;
forming a material stack on a portion of the first metal material;
removing a portion of the material stack to form a common gate region;
forming a first isolation material on a portion of the first metal material;
forming a gate dielectric material on a portion of the material stack;
forming a common gate conductive material in a portion of the common gate region, wherein the common gate conductive material is common to each of the cells of the array of memory cells;
forming a dielectric material on the common gate conductive material; and
forming a second metal material on a portion of the material stack.

### Claim 2 (depends on 1)

The method of claim 1, wherein the material stack includes a base semiconductor material and a resistive storage element.

### Claim 3 (depends on 2)

The method of claim 2, wherein the material stack includes a first doped semiconductor material and a second doped semiconductor material.

### Claim 4 (depends on 3)

The method of claim 3, wherein the base semiconductor material is an undoped semiconductor material.

### Claim 5 (depends on 1)

The method of claim 1, wherein the gate dielectric material has a thickness from about 20 angstroms to about 70 angstroms.

### Claim 6 (depends on 1)

The method of claim 1, wherein the gate dielectric material is formed conformally on the portion of the material stack.

### Claim 7

A method of forming an array of memory cells, the method comprising:
forming a first doped semiconductor material on a portion of a first metal material;
forming a material stack on a portion of the first doped semiconductor material, wherein the material stack includes a first isolation material, a common gate conductive material, and a second isolation material, wherein the common gate conductive material is common to each of the memory cells of the array;
removing a portion of the material stack;
forming a gate dielectric material on a portion of the common gate conductive material;
forming a base semiconductor material on a portion of the gate dielectric material;
forming a second doped semiconductor material on a portion of the base semiconductor material; and
forming a resistive storage element on a portion of the second doped semiconductor material.

### Claim 8 (depends on 7)

The method of claim 7, further including forming a second metal material on a portion of the material stack.

### Claim 9 (depends on 7)

The method of claim 7, wherein the first doped semiconductor material is a heavily doped semiconductor material.

### Claim 10 (depends on 7)

The method of claim 7, wherein the second doped semiconductor material is a heavily doped semiconductor material.

### Claim 11 (depends on 7)

The method of claim 7, wherein the common gate conductive material is continuous.

### Claim 12 (depends on 7)

The method of claim 7, wherein the common gate conductive material surrounds the base semiconductor material.

### Claim 13

A method of forming a device, the method comprising:
forming a first array including a first group of memory cells, each including a resistive storage element coupled to a select device, wherein the group includes at least three memory cells such that at least two of the three memory cells are physically connected to a first sense line and at least two of the three memory cells are physically connected to a first access line;
wherein each select device includes a base semiconductor material, a first terminal, a second terminal, and a first group gate terminal; and
wherein the first group gate terminal of each select device is common to each memory cell of the first group and is common to each of the cells of the first array of memory cells.

### Claim 14 (depends on 13)

The method of claim 13, wherein each select device is bipolar.

### Claim 15 (depends on 13)

The method of claim 13, wherein each cell of the first group of memory cells has an area that is 4F2.

### Claim 16 (depends on 13)

The method of claim 13, further comprising:
forming a second array including a second group of memory cells coupled to the first group, wherein each cell of the second group each includes a resistive storage element coupled to a select device that includes a first terminal, a second terminal, and a second group gate terminal, which is common to each memory cell of the second group.

### Claim 17 (depends on 16)

The method of claim 16, wherein the first group gate terminal is configured to receive a first common gate voltage and the second group gate terminal is configured to receive a second common gate voltage, wherein the first common gate voltage and second common gate voltage have differing values.