# US 9,520,436 B2 · Solid-state imaging device and manufacturing method thereof

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- Number: US 9,520,436 B2
- Document ID: US9520436B2
- Status: Granted
- Kind: B2
- Application number: 15/069,542
- Filed: 2016-03-14
- Published: 2016-09-22
- Granted: 2016-12-13
- Earliest claimed: 2015-03-19
- Assignees: Dexerials Corporation
- Applicants: Seiko Epson Corporation
- Inventors: Kazunobu Kuwazawa; Noriyuki Nakamura; Mitsuo Sekisawa; Takehiro Endo
- Web page: https://patentgrep.com/patent/US9520436B2

## CPC

- H10F 39/18: Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
- H04N 25/00: Circuitry of solid-state image sensors [SSIS]; Control thereof
- H10D 62/60: Impurity distributions or concentrations
- H10F 39/014: {of CMOS image sensors}
- H10F 39/80: {Constructional details of image sensors}
- H10F 39/802: {Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes}
- H10F 39/8027: {Geometry of the photosensitive area}
- H10F 39/8033: {Photosensitive area}
- H10F 39/8037: {the integrated elements comprising a transistor}
- H10F 39/80373: {characterised by the gate of the transistor}
- H10F 39/80377: {characterised by the channel of the transistor, e.g. channel having a doping gradient}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10P 30/22: using masks
- H10P 30/221: {characterised by the angle between the ion beam and the mask}
- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A solid-state imaging device includes a P-well, a gate insulating film, a gate electrode, a P+-type pinning layer that is located in the P-well so as to be outside the gate electrode and start from a first end portion of the gate electrode, a P−-type impurity region that is located in the P-well so as to extend under the gate electrode from a first end portion side and be in contact with the pinning layer, an N−-type impurity region that is located in the semiconductor layer under the P−-type impurity region and includes a portion that is under the pinning layer, and an N−-type impurity region that is in contact with the gate insulating film and the P−-type impurity region and is located so as to surround the N−-type impurity region in plan view.

## Claims

### Claim 1

A solid-state imaging device comprising:
a first conductivity type semiconductor layer;
a gate insulating film located on the semiconductor layer;
a gate electrode located on the gate insulating film;
a first conductivity type first impurity region that is located in the semiconductor layer so as to be outside the gate electrode and start from a first end portion of the gate electrode in plan view;
a first conductivity type second impurity region that is located in the semiconductor layer so as to extend under the gate electrode from a first end portion side and be in contact with the first impurity region;
a second conductivity type third impurity region that is located in the semiconductor layer under the second impurity region and includes a portion that is under the first impurity region;
a second conductivity type fifth impurity region that is located in the semiconductor layer so as to extend under the first impurity region and the third impurity region, be in contact with the gate insulating film and the second impurity region, and surround the third impurity region in plan view; and
a second conductivity type fourth impurity region that is located in the semiconductor layer and includes a portion that is under a second end portion of the gate electrode,
wherein the first impurity region, the second impurity region, the fifth impurity region, and the semiconductor layer are located in the stated order from the outside of the gate electrode on the first end portion side toward the second end portion of the gate electrode in plan view, impurity concentration in the first impurity region, the second impurity region, and the semiconductor layer decreases in the stated order, and impurity concentration in the fifth impurity region is lower than that of the third impurity region.

### Claim 2 (depends on 1)

The solid-state imaging device according to claim 1, wherein the second impurity region includes a portion that is located under the first impurity region.

### Claim 3 (depends on 1)

The solid-state imaging device according to claim 1, wherein the second impurity region does not exist outside of the gate electrode from the first end portion in plan view.

### Claim 4 (depends on 1)

The solid-state imaging device according to claim 1, wherein the third impurity region overlaps with the fifth impurity region in plan view.

### Claim 5 (depends on 1)

The solid-state imaging device according to claim 1, wherein the fifth impurity region is in contact with the first impurity region and the third impurity region.

### Claim 6 (depends on 1)

The solid-state imaging device according to claim 1,
wherein the semiconductor layer is a first conductivity type well, and
the first conductivity type well is located in a semiconductor substrate.

### Claim 7 (depends on 1)

The solid-state imaging device according to claim 1, wherein the semiconductor layer is a first conductivity type semiconductor substrate.

### Claim 8

A manufacturing method of a solid-state imaging device comprising:
forming a second conductivity type fifth impurity region in a first conductivity type semiconductor layer by forming a photoresist on the semiconductor layer and implanting a second conductivity type impurity ion in a first direction using the photoresist as a mask;
forming a first conductivity type second impurity region in the semiconductor layer on a surface side of the semiconductor layer so as to be in contact with the fifth impurity region by implanting a first conductivity type impurity ion in a second direction using the photoresist as a mask;
removing the photoresist;
forming a second conductivity type third impurity region under the second impurity region in the fifth impurity region on a surface side of the fifth impurity region;
forming a gate insulating film on the semiconductor layer;
forming a gate electrode on the gate insulating film;
forming a first conductivity type first impurity region in the semiconductor layer so as to be outside the gate electrode and start from the first end portion of the gate electrode in plan view by implanting a first conductivity type impurity ion using the gate electrode as a mask, the first end portion of the gate electrode serving as a first mask end portion; and
forming a second conductivity type fourth impurity region in the semiconductor layer that is located in the semiconductor layer and includes a portion that is under a second end portion of the gate electrode by implanting a second conductivity type impurity ion using the gate electrode as a mask, the second end portion of the gate electrode serving as a second mask end portion,
wherein the second impurity region is in contact with the first impurity region and is formed in the semiconductor layer so as to extend under the gate electrode from a first end portion side,
the first impurity region, the second impurity region, the fifth impurity region, and the semiconductor layer are located in the stated order from the outside of the gate electrode on the first end portion side toward the second end portion of the gate electrode in plan view,
the fifth impurity region is located so as to extend under the first impurity region and the third impurity region and surround the third impurity region in plan view,
impurity concentration in the first impurity region, the second impurity region, and the semiconductor layer decreases in the stated order, and impurity concentration in the fifth impurity region is lower than that of the third impurity region,
the first direction is a direction inclined relative to a vertical direction to a surface of the semiconductor layer, and
the second direction is a direction closer to the vertical direction than the first direction is.

### Claim 9

A manufacturing method of a solid-state imaging device comprising:
forming a second conductivity type fifth impurity region in a first conductivity type semiconductor layer,
forming a second conductivity type third impurity region in the semiconductor layer so as to have a smaller depth than the fifth impurity region,
forming a gate insulating film on the semiconductor layer;
forming a gate electrode on the gate insulating film;
forming a first conductivity type second impurity region in the semiconductor layer by implanting a first conductivity type impurity ion in a first direction using the gate electrode as a mask, a first end portion of the gate electrode serving as a first mask end portion;
forming a first conductivity type first impurity region that is located in the semiconductor layer so as to be outside the gate electrode and start from a first end portion of the gate electrode in plan view by implanting a first conductivity type impurity ion in a second direction using the gate electrode as a mask, the first end portion of the gate electrode serving as the first mask end portion; and
forming a second conductivity type fourth impurity region in the semiconductor layer that is located in the semiconductor layer and includes a portion that is under a second end portion of the gate electrode by implanting a second conductivity type impurity ion using the gate electrode as a mask, a second end portion of the gate electrode serving as a second mask end portion,
wherein the second impurity region is in contact with the first impurity region and is formed in the semiconductor layer so as to extend under the gate electrode from the first end portion side,
the first impurity region, the second impurity region, the fifth impurity region, and the semiconductor layer are located in the stated order from the outside of the gate electrode on the first end portion side toward the second end portion of the gate electrode in plan view,
the fifth impurity region is located so as to extend under the first impurity region and the third impurity region and surround the third impurity region in plan view,
impurity concentration in the first impurity region, the second impurity region, and the semiconductor layer decreases in the stated order, and impurity concentration in the fifth impurity region is lower than that of the third impurity region,
the first direction is a direction inclined relative to a vertical direction to a surface of the semiconductor layer, and
the second direction is a direction closer to the vertical direction than the first direction is.