# US 9,520,430 B2 · Solid state imaging apparatus, production method thereof and electronic device

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- Number: US 9,520,430 B2
- Document ID: US9520430B2
- Status: Granted
- Kind: B2
- Application number: 14/319,941
- Filed: 2014-06-30
- Published: 2015-01-08
- Granted: 2016-12-13
- Earliest claimed: 2013-07-05
- Assignees: Sony Corporation
- Applicants: Sony Corporation
- Inventors: Kyohei Mizuta; Tomokazu Ohchi; Yohei Chiba
- Web page: https://patentgrep.com/patent/US9520430B2

## CPC

- H10F 77/241: {comprising ring electrodes}
- H10F 39/018: {of hybrid image sensors}
- H10F 39/024: {of coatings or optical elements}
- H10F 39/026: {Wafer-level processing}
- H10F 39/182: {Colour image sensors}
- H10F 39/199: {Back-illuminated image sensors}
- H10F 39/805: {Coatings}
- H10F 39/8053: {Colour filters}
- H10F 39/8057: {Optical shielding}
- H10F 39/8063: {Microlenses}
- H10F 39/8067: {Reflectors}
- H10F 39/807: {Pixel isolation structures}
- H10F 39/809: {of hybrid image sensors}
- H10F 39/811: {Interconnections}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/2125: {Top-view shapes}
- H10W 20/217: {comprising ring-shaped isolation structures outside of the via holes}
- H04N 25/616: involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/46: comprising air gaps
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION

## Abstract

A solid state imaging apparatus includes an insulation structure formed of an insulation substance penetrating through at least a silicon layer at a light receiving surface side, the insulation structure having a forward tapered shape where a top diameter at an upper portion of the light receiving surface side of the silicon layer is greater than a bottom diameter at a bottom portion of the silicon layer. Also, there are provided a method of producing the solid state imaging apparatus and an electronic device including the solid state imaging apparatus.

## Claims

### Claim 1

A solid state imaging apparatus, comprising:
a first semiconductor substrate, wherein at least a photodiode is formed in the first semiconductor substrate;
a second semiconductor substrate, wherein at least a logic circuit is formed in the second semiconductor substrate, and wherein the first semiconductor substrate is bonded to the second semiconductor substrate,
an insulation structure formed of an insulation material penetrating through at least a silicon layer of the first semiconductor substrate from a light receiving surface side,
wherein the insulation material of the insulation structure includes at least one of hafnium oxide and silicon oxide,
wherein the insulation structure is a chip surrounding guard ring disposed at a side of a scribe area, and
wherein the insulation structure is disposed above a wiring layer of the second semiconductor substrate.

### Claim 2 (depends on 1)

The solid state imaging apparatus according to claim 1, wherein
the insulation structure includes a material used for an antireflection film, a Si compound, a copolymerization based resin material used for an on-chip lens and an air gap.

### Claim 3 (depends on 1)

The solid state imaging apparatus according to claim 1, wherein
the insulation structure is trenched to connect to a wiring layer of the second semiconductor substrate.

### Claim 4 (depends on 1)

The solid state imaging apparatus according to claim 1, wherein
the insulation structure is trenched to connect to a silicon layer of the second semiconductor substrate.

### Claim 5 (depends on 1)

The solid state imaging apparatus according to claim 1, wherein the insulation structure is a first insulation structure, wherein the solid state imaging apparatus further comprises a second insulation structure, and
wherein a connection conductor filled between the first and second insulation structures has a shared contact structure that is connected to both of a wiring layer of the first semiconductor substrate and a wiring layer of the second semiconductor substrate.

### Claim 6 (depends on 1)

The solid state imaging apparatus according to claim 1, wherein
the insulation structure extends to an isolated pad.

### Claim 7 (depends on 1)

The solid state imaging apparatus of claim 1,
wherein the insulation material is a same material as one of an antireflection film, an insulation film, and an on-chip lens.

### Claim 8 (depends on 1)

The solid state imaging apparatus of claim 1,
wherein the insulation material is formed of an antireflection film material.

### Claim 9 (depends on 1)

The solid state imaging apparatus of claim 1,
wherein the insulation material is formed of an insulation film material.

### Claim 10 (depends on 1)

The solid state imaging apparatus of claim 1,
wherein the insulation material is at least partially formed of a resin material.

### Claim 11

An electronic device, comprising:
a solid state imaging apparatus, including:
a first semiconductor substrate, wherein at least a photodiode is formed in the first semiconductor substrate,
a second semiconductor substrate, wherein at least a logic circuit is formed in the second semiconductor substrate, and wherein the first semiconductor substrate is bonded to the first semiconductor substrate;
an insulation structure formed of a solid insulation substance penetrating through at least a silicon layer of the first semiconductor substrate from a light receiving surface side, wherein the insulation structure is a chip surrounding guard ring disposed at a side of a scribe area, and wherein the insulation structure is disposed above a wiring layer of the second semiconductor substrate.