# US 9,520,425 B2 · Image sensors with small pixels having high well capacity > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,520,425 B2 - Document ID: US9520425B2 - Status: Granted - Kind: B2 - Application number: 14/189,382 - Filed: 2014-02-25 - Published: 2014-09-04 - Granted: 2016-12-13 - Earliest claimed: 2013-03-01 - Assignees: Semiconductor Components Industries, LLC - Applicants: Semiconductor Components Industries, LLC - Inventors: Jaroslav Hynecek - Web page: https://patentgrep.com/patent/US9520425B2 ## CPC - H10F 39/8033: {Photosensitive area} - H10F 39/014: {of CMOS image sensors} - H10F 39/199: {Back-illuminated image sensors} - H10F 39/8037: {the integrated elements comprising a transistor} - H10F 39/807: {Pixel isolation structures} - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION ## Abstract An image sensor having small pixels with high charge storage capacity, low dark current, no image lag, and good blooming control may be provided. The high charge storage capacity is achieved by placing a p+ type doped layer under the pixel charge storage region with an opening in it for allowing photo-generated charge carriers to flow from the silicon hulk to the charge storage well located near the surface of the photodiode. A compensating n-type doped implant may be formed in the opening. Image lag is prevented by placing a p− type doped region under the p+ type doped photodiode pinning layer and aligned with the opening. Blooming control is achieved by adjusting the length of the transfer gate in the pixel and thereby adjusting the punch-through potential under the gate. ## Claims ### Claim 1 An image sensor pixel in a pixel array having a silicon substrate, comprising: a photodiode formed in a surface of the silicon substrate, wherein the silicon substrate includes a bulk portion under the photodiode; a p+ type doped layer that extends under the photodiode parallel to the surface, wherein the p+ type doped layer comprises an opening through which charge carriers pass from the bulk portion of the silicon substrate to the photodiode; and a compensating n-type doped implant region in the opening. ### Claim 2 (depends on 1) The image sensor pixel defined in claim 1 further comprising a p-type doped implant region interposed between the photodiode and the compensating n-type doped implant region, wherein the p-type doped implant region is aligned with the compensating n-type doped implant region. ### Claim 3 (depends on 2) The image sensor pixel defined in claim 2 wherein the p-type doped layer is connected to ground. ### Claim 4 (depends on 2) The image sensor pixel defined in claim 2 further comprising: a transfer gate formed on the surface of the silicon substrate; a punch-through region under the transfer gate; and a blooming control structure formed at least partially from the punch-through region under the transfer gate. ### Claim 5 (depends on 4) The image sensor pixel defined in claim 4 wherein the transfer gate has a length and wherein a pixel blooming level is determined based on the length of the transfer gate. ### Claim 6 (depends on 5) The image sensor pixel defined in claim 5 wherein the length of the transfer gate of the image sensor pixel is different than that of transfer gates of other image sensor pixels in the pixel array. ### Claim 7 (depends on 5) The image sensor pixel defined in claim 5 wherein the length of the transfer gate is determined based on an expected light intensity overload. ### Claim 8 (depends on 2) The image sensor pixel defined in claim 2 further comprising a plurality of n-type doped regions formed in the bulk portion of the silicon substrate, wherein the plurality of n-type doped regions form a potential gradient that directs charge carriers from the bulk portion of the silicon substrate through the opening. ### Claim 9 (depends on 2) The image sensor pixel defined in claim 2 further comprising a plurality of pixel separation implants that separate the image sensor pixel from other image sensor pixels in the pixel array. ### Claim 10 (depends on 1) The image sensor pixel defined in claim 1 wherein the image sensor pixel is a backside illuminated image sensor pixel. ### Claim 11 An image sensor having an array of image sensor pixels and a silicon substrate, the image sensor comprising: a plurality of photodiodes formed in a surface of the silicon substrate, wherein the silicon substrate includes a bulk portion under the plurality of photodiodes; a p+ type doped layer that extends under the plurality of photodiodes parallel to the surface, wherein the p+ type doped layer comprises a plurality of openings through which charge carriers pass from the bulk portion of the silicon substrate he photodiodes; and a plurality of compensating n-type doped implant regions, wherein each compensating n-type doped implant region is formed in a respective one of the openings. ### Claim 12 (depends on 11) The image sensor defined in claim 11 further comprising a plurality of p-type doped implant regions, wherein each p-type doped implant region is interposed between a respective one of the photodiodes and a respective one of the compensating n-type doped implant regions, wherein each p-type doped implant region is aligned with the respective compensating n-type doped implant region. ### Claim 13 (depends on 12) The image sensor defined in claim 12 wherein the p-type doped layer is connected to ground. ### Claim 14 (depends on 12) The image sensor defined in claim 12 further comprising a plurality of transfer gates formed on the surface of the silicon substrate; a punch-through region under each transfer gate; and a plurality of blooming control structures, wherein each blooming control structure is formed at least partially from the punch-through region under a respective one of the transfer gates. ### Claim 15 A system, comprising: a central processing unit; memory; input-output circuitry; and an image sensor pixel in a pixel array having a silicon substrate, comprising: a photodiode thrilled in a surface of the silicon substrate, wherein the silicon substrate includes a bulk portion under the photodiode; a p+ type doped layer that extends under the photodiode parallel to the surface, wherein the p+ type doped layer comprises an opening through which charge carriers pass from the bulk portion of the silicon substrate to the photodiode; and a compensating n-type doped implant region in the opening. ### Claim 16 (depends on 15) The system defined in claim 15 further comprising a p-type doped implant region interposed between the photodiode and the compensating n-type doped implant region, wherein the p-type doped implant region is aligned with the compensating n-type doped implant region. ### Claim 17 (depends on 16) The system defined in claim 16 wherein the p-type doped layer is connected to around. ### Claim 18 (depends on 16) The system defined in claim 16 further comprising: a transfer gate formed on the surface of the silicon substrate; a punch-through region under the transfer gate; and a blooming control structure formed at least partially from the punch-through region under the transfer gate. ### Claim 19 (depends on 18) The system defined in claim 18 wherein the transfer gate has a length and wherein a pixel blooming level is determined based on the length of the transfer gate. ### Claim 20 (depends on 19) The image sensor pixel defined in claim 19 wherein the length of the transfer gate of the image sensor pixel is different than that of transfer gates of other image sensor pixels in the pixel array.