# US 9,520,420 B2 · Method for manufacturing array substrate, array substrate, and display device

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- Number: US 9,520,420 B2
- Document ID: US9520420B2
- Status: Granted
- Kind: B2
- Application number: 14/402,532
- Filed: 2013-12-16
- Published: 2015-11-26
- Granted: 2016-12-13
- Earliest claimed: 2013-07-17
- Assignees: Boe Technology Group Co., Ltd.
- Applicants: Boe Technology Group Co., Ltd.
- Inventors: Zheng Liu; Jangsoon Im; Zuqiang Wang
- Web page: https://patentgrep.com/patent/US9520420B2

## CPC

- H10D 86/0223: {comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials}
- H10D 86/0212: {comprising manufacture, treatment or coating of substrates}
- H10D 86/0229: {characterised by control of the annealing or irradiation parameters}
- H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present invention provides a method for manufacturing an array substrate, an array substrate, and a display device. The method for manufacturing an array substrate, including a step of forming a thin film transistor and a storage capacitor on a substrate, the thin film transistor including a gate, a source, and a drain, and the storage capacitor including a first pole plate and a second pole plate, wherein, arranging the source, the drain, and the first pole plate in a single layer through implanting dopant ions into an amorphous silicon layer formed on the substrate by one ion-implantation process, and through crystallizing an amorphous silicon material forming the amorphous silicon layer and activating the dopant ions by a laser irradiation process. Accordingly, process steps are simplified and a process cost is reduced greatly, and the performances of the array substrate and the display device are increased.

## Claims

### Claim 1

A method for manufacturing an array substrate, including a step of forming a thin film transistor and a storage capacitor on a substrate, the thin film transistor including a gate, a source, and a drain, and the storage capacitor including a first pole plate and a second pole plate, wherein, arranging the source, the drain, and the first pole plate in a single layer firstly through implanting dopant ions into an amorphous silicon layer formed on the substrate by one ion-implantation process, and then through crystallizing an amorphous silicon material forming the amorphous silicon layer and activating the dopant ions by a laser irradiation process.

### Claim 2 (depends on 1)

The method according to claim 1, wherein, the step of forming a thin film transistor and a storage capacitor on a substrate includes the following steps:
step S10: forming a buffer layer on the substrate;
step S11: forming the amorphous silicon layer on the buffer layer, and performing a patterning process on the amorphous silicon layer to form a pattern including an amorphous silicon island;
step S12: on the substrate subjected to the step S11, forming a photoresist mask by using a photoresist, setting a to-be-doped region in the amorphous silicon island, and implanting the dopant ions into the to-be-doped region by the one ion-implantation process, wherein, the to-be-doped region includes a source region to be formed into the source, a drain region to be formed into the drain, and a pole plate region to be formed into the first pole plate;
step S13: on the substrate subjected to the step S12, irradiating the amorphous silicon island by the laser irradiation process to convert the amorphous silicon island into a polysilicon island and activate the dopant ions in the source, the drain, and the first pole plate; and
step S14: on the substrate subjected to the step S13, forming a pattern including a gate insulating layer, the gate, and the second pole plate, so that the gate at least partially overlaps the source and the drain in an orthogonal projection direction, and the second pole plate at least partially overlaps the first pole plate in the orthogonal projection direction.

### Claim 3 (depends on 2)

The method according to claim 2, wherein, the step of forming a photoresist mask by using a photoresist, setting a to-be-doped region in the amorphous silicon island, and implanting the dopant ions into the to-be-doped region by the one ion-implantation process include the following steps:
step S30: forming a layer of photoresist on the substrate on which the pattern including the amorphous silicon island is formed;
step S31: exposing the photoresist by using a mask plate and developing the photoresist, so that portions of the photoresist which correspond to the source region, the drain region, and the pole plate region are removed completely, and other portion of the photoresist is reserved completely;
step S32: implanting the dopant ions into the source region, the drain region, and the pole plate region by the one ion-implantation process; and
step S33: stripping off remaining photoresist.

### Claim 4 (depends on 2)

The method according to claim 2, wherein, the laser irradiation process is an excimer laser process, the laser irradiation process includes two laser irradiation treatments, a first laser irradiation treatment causes the amorphous silicon island to be crystallized and converted into a polysilicon island, a second laser irradiation treatment actives the dopant ions implanted into the polysilicon island by the ion-implantation process to active the dopant ions in the source, the drain, and the first pole plate.

### Claim 5 (depends on 4)

The method according to claim 4, wherein, a laser used in the excimer laser process includes an ArF laser, a KrF laser, or an XeCl laser, the ArF laser has a wavelength of 193 nm, the KrF laser has a wavelength of 248 nm, and the XeCl laser has a wavelength of 308 nm, and the ArF laser, the KrF laser, and the XeCl laser have a pulse width range of 10-50 ns.

### Claim 6 (depends on 2)

The method according to claim 2, further including the following step:
forming an interlayer insulating layer and a pattern including an extraction electrode on the substrate on which the thin film transistor and the storage capacitor are formed, so that the extraction electrode includes a first electrode and a second electrode, the interlayer insulating layer are provided with a first via and a second via at regions which correspond to the source and the drain respectively, the source is electrically connected to the first electrode through the first via, and the drain is electrically connected to the second electrode through the second via.

### Claim 7 (depends on 1)

The method according to claim 1, wherein, the step of forming a thin film transistor and a storage capacitor on a substrate includes the following steps:
step S20: forming a buffer layer on the substrate;
step S21: forming a pattern including the gate, the second pole plate, and a gate insulating layer on the buffer layer;
step S22: forming the amorphous silicon layer on the substrate subjected to the step S21, and performing a patterning process on the amorphous silicon layer to form a pattern including an amorphous silicon island;
step S23: on the substrate subjected to the step S22, forming a photoresist mask by using a photoresist, setting a to-be-doped region in the amorphous silicon island, and implanting the dopant ions into the to-be-doped region by the one ion-implantation process, wherein, the to-be-doped region includes a source region to be formed into the source, a drain region to be formed into the drain, and a pole plate region to be formed into the first pole plate, the gate at least partially overlaps the source and the drain in an orthogonal projection direction, and the second pole plate at least partially overlaps the first pole plate in the orthogonal projection direction; and
step S24: on the substrate subjected to the step S23, irradiating the amorphous silicon island by the laser irradiation process to convert the amorphous silicon island into a polysilicon island and activate the dopant ions in the source, the drain, and the first pole plate.

### Claim 8 (depends on 7)

The method according to claim 7, wherein, the step of forming a photoresist mask by using a photoresist, setting a to-be-doped region in the amorphous silicon island, and implanting the dopant ions into the to-be-doped region by the one ion-implantation process include the following steps:
step S30: forming a layer of photoresist on the substrate on which the pattern including the amorphous silicon island is formed;
step S31: exposing the photoresist by using a mask plate and developing the photoresist, so that portions of the photoresist which correspond to the source region, the drain region, and the pole plate region are removed completely, and other portion of the photoresist is reserved completely;
step S32: implanting the dopant ions into the source region, the drain region, and the pole plate region by the one ion-implantation process; and
step S33: stripping off remaining photoresist.

### Claim 9 (depends on 7)

The method according to claim 7, wherein, the laser irradiation process is an excimer laser process, the laser irradiation process includes two laser irradiation treatments, a first laser irradiation treatment causes the amorphous silicon island to be crystallized and converted into a polysilicon island, a second laser irradiation treatment actives the dopant ions implanted into the polysilicon island by the ion-implantation process to active the dopant ions in the source, the drain, and the first pole plate.

### Claim 10 (depends on 9)

The method according to claim 9, wherein, a laser used in the excimer laser process includes an ArF laser, a KrF laser, or an XeCl laser, the ArF laser has a wavelength of 193 nm, the KrF laser has a wavelength of 248 nm, and the XeCl laser has a wavelength of 308 nm, and the ArF laser, the KrF laser, and the XeCl laser have a pulse width range of 10-50 ns.

### Claim 11 (depends on 7)

The method according to claim 7, further including the following step:
forming an interlayer insulating layer and a pattern including an extraction electrode on the substrate on which the thin film transistor and the storage capacitor are formed, so that the extraction electrode includes a first electrode and a second electrode, the interlayer insulating layer are provided with a first via and a second via at regions which correspond to the source and the drain respectively, the source is electrically connected to the first electrode through the first via, and the drain is electrically connected to the second electrode through the second via.

### Claim 12 (depends on 1)

The method according to claim 1, wherein, the ion-implantation process includes an ion-implantation process with a mass analyzer, an ion cloud type implantation process without a mass analyzer, a plasma implantation process, or a solid-state diffusion implantation process, wherein, an implantation medium is a gas including a boron element and/or a phosphorus element, an implantation energy is in a range of 10-200 keV, and an implantation dose is in a range of 1×1011-1×1020 atoms/cm3.