# US 9,520,419 B2 · Thin film transistor array substrate and manufacturing method thereof

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- Number: US 9,520,419 B2
- Document ID: US9520419B2
- Status: Granted
- Kind: B2
- Application number: 14/793,183
- Filed: 2015-07-07
- Published: 2015-10-29
- Granted: 2016-12-13
- Earliest claimed: 2010-01-14
- Assignees: Samsung Display Co., Ltd.
- Applicants: Samsung Display Co., Ltd.
- Inventors: Young-Wook Lee; Woo-Geun Lee; Ki-Won Kim; Hyun-Jung Lee; Ji-Soo Oh
- Web page: https://patentgrep.com/patent/US9520419B2

## CPC

- H10D 86/60: wherein the TFTs are in active matrices
- H10D 30/6756: {Amorphous oxide semiconductors}
- H10D 86/0212: {comprising manufacture, treatment or coating of substrates}
- H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies}
- H10D 86/0231: {using masks, e.g. half-tone masks}
- H10D 86/411: {characterised by materials, geometry or structure of the substrates}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of manufacturing a thin film transistor (TFT) array substrate includes forming a gate line and a gate electrode on a substrate, forming a gate-insulating layer and an oxide semiconductor layer on the gate line and the gate electrode, forming etch stop patterns at a thin-film transistor area and an area where the gate line and the data line overlap each other, forming a data conductor on the oxide semiconductor layer and the etch stop patterns, the data conductor comprising a source electrode and a drain electrode that constitute a TFT together with the gate electrode, and forming a data line extending in a direction intersecting the gate line.

## Claims

### Claim 1

A method of manufacturing a thin film transistor (TFT) array substrate, the method comprising:
forming a gate line and a gate electrode on a substrate;
forming a gate-insulating layer and an oxide semiconductor layer on the gate line and the gate electrode;
forming etch stop patterns at a TFT area and an area where the gate line and the data line overlap each other;
forming a data conductor on the oxide semiconductor layer and the etch stop patterns, the data conductor comprising a source electrode and a drain electrode that constitute a TFT together with the gate electrode; and
forming a data line extending in a direction intersecting the gate line.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming a storage electrode disposed on the same layer as the gate line and the gate electrode; and
forming an etch stop pattern of the etch stop patterns at an area where the storage electrode and the data line overlap each other.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
forming oxide semiconductor layer patterns at least on the gate electrode by patterning the oxide semiconductor layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein forming the data line comprises:
forming a conductive layer; and
patterning the conductive layer,
wherein in patterning of the conductive layer, the oxide semiconductor layer is patterned together with the conductive layer to form an oxide semiconductor layer pattern.

### Claim 5 (depends on 1)

The method of claim 1, wherein the etch stop patterns comprise at least one of silicon oxide (SiOx) and silicon nitride (SiNx).

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
forming a low-k dielectric material layer,
wherein in forming the etch stop patterns, the low-k dielectric material layer is patterned together with an etch stop layer to form the low-k dielectric material pattern on or under the etch stop patterns.

### Claim 7 (depends on 6)

The method of claim 6, wherein the low-k dielectric material layer comprises at least one of SiBN, SiCN, BCN, BN, and CN.

### Claim 8 (depends on 6)

The method of claim 6, wherein forming the low-k dielectric material layer comprises forming the low-k dielectric material layer to be thicker than the etch stop layer.

### Claim 9 (depends on 1)

The method of claim 1, wherein forming the etch stop patterns comprises:
forming a transparent organic layer pattern on an etch stop layer; and
patterning the etch stop layer using the transparent organic layer pattern as a patterning mask,
wherein the data line is formed while the transparent organic layer pattern is not removed.