# US 9,520,412 B2 · Thin film transistor panel having an etch stopper on semiconductor

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- Number: US 9,520,412 B2
- Document ID: US9520412B2
- Status: Granted
- Kind: B2
- Application number: 14/798,123
- Filed: 2015-07-13
- Published: 2015-11-05
- Granted: 2016-12-13
- Earliest claimed: 2010-02-11
- Assignees: Samsung Display Co., Ltd.
- Applicants: Samsung Display Co., Ltd.
- Inventors: Pil-Sang Yun; Ki-Won Kim; Hye-Young Ryu; Woo-Geun Lee; Seung-Ha Choi; Jae-Hyoung Youn; Kyoung-Jae Chung; Young-Wook Lee; Je-Hun Lee; Kap-Soo Yoon; Do-Hyun Kim; Dong-Ju Yang; Young-Joo Choi
- Web page: https://patentgrep.com/patent/US9520412B2

## CPC

- H10D 30/6729: {characterised by the electrodes}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/6704: {having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 64/011: {of electrodes ohmically coupled to a semiconductor}
- H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies}
- H10D 86/0231: {using masks, e.g. half-tone masks}
- H10D 86/40: characterised by multiple TFTs
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10P 14/61: using masks
- H10P 50/20: Dry etching; Plasma etching; Reactive-ion etching
- H10P 50/282: {of inorganic materials}
- H10P 52/00: Grinding, lapping or polishing of wafers, substrates or parts of devices
- H10P 95/00: Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10P 95/70: Chemical treatments
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.

## Claims

### Claim 1

A method for forming a panel comprising a thin film transistor, the method comprising:
forming an oxide semiconductor pattern comprising a channel region;
forming an etch stopper at a position corresponding to the channel region; and
forming a first electrode and a second electrode spaced apart from the first electrode, the channel region configured to connect the first electrode to the second electrode,
wherein the oxide semiconductor pattern, the first electrode, and the second electrode are formed using a first mask, and
wherein a work function of at least one of the first electrode and the second electrode is lower than a work function of the oxide semiconductor pattern.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
disposing a first conductive layer on a substrate;
disposing a first insulating layer on the first conductive layer;
disposing an oxide semiconductor layer on the first insulating layer;
disposing a second conductive layer on the etch stopper and the oxide semiconductor layer;
wherein the oxide semiconductor layer and the second conductive layer are patterned using the first mask to form the oxide semiconductor pattern, the first electrode, and the second electrode.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
forming a second insulating layer on the first electrode and the second electrode;
patterning the second insulating layer to form a contact hole exposing the first electrode; and
forming a third conductive layer on the second insulating layer;
patterning the third conductive layer to form a third electrode,
wherein the third electrode is connected to the first electrode via the contact hole.

### Claim 4 (depends on 3)

The method of claim 3, wherein the second insulating layer comprises a passivation layer.

### Claim 5 (depends on 3)

The method of claim 3, wherein the second insulating layer comprises a color filter.

### Claim 6 (depends on 3)

The method of claim 3, further comprising:
patterning the first conductive layer to form a fourth electrode, the fourth electrode being disposed under the etch stopper and the oxide semiconductor pattern.

### Claim 7 (depends on 6)

The method of claim 6, wherein forming the etch stopper comprises disposing an etch stopper layer on the oxide semiconductor layer and patterning the etch stopper layer.

### Claim 8 (depends on 7)

The method of claim 7, wherein the etch stopper is formed by dry etching the etch stopper layer.

### Claim 9 (depends on 7)

The method of claim 7, wherein the first conductive layer is patterned using a second mask, the etch stopper layer is patterned using a third mask, the second insulating layer is patterned using a fourth mask, and the third conductive layer is patterned using a fifth mask.

### Claim 10 (depends on 2)

The method of claim 2, wherein the oxide semiconductor pattern, the first electrode, and the second electrode are formed by wet etching the second conductive layer and the oxide semiconductor layer.