# US 9,520,409 B2 · Three-dimensional nonvolatile memory device, semiconductor system including the same, and method of manufacturing the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 9,520,409 B2
- Document ID: US9520409B2
- Status: Granted
- Kind: B2
- Application number: 15/016,425
- Filed: 2016-02-05
- Published: 2016-06-09
- Granted: 2016-12-13
- Earliest claimed: 2014-05-23
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Tae Kyung Kim; Dae Sung Eom
- Web page: https://patentgrep.com/patent/US9520409B2

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- G11C 16/06: Auxiliary circuits, e.g. for writing into memory
- H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A three-dimensional nonvolatile memory device includes a first vertical channel layer and a second vertical channel layer extending from a substrate, a plurality of memory cells, first selection transistors and second selection transistors spaced apart from each other along the first vertical channel layer and the second vertical channel layer, a pad, a contact plug and a bit line in a stacked configuration over the first vertical channel layer, and a common source line formed over the second vertical channel layer.

## Claims

### Claim 1

A method of manufacturing a three-dimensional nonvolatile memory device, the method comprising:
depositing a plurality of interlayer insulating layers and a plurality of sacrificial layers in a stacked configuration along first vertical channel layers and second vertical channel layers, wherein the first and second vertical channel layers extend from a substrate;
etching portions of the plurality of the interlayer insulating layers and the plurality of sacrificial layers to form a slit, wherein portions of the sacrificial layers are exposed through a sidewall of the slit;
removing the portions of the sacrificial layers exposed by the slit to form recesses between the interlayer insulating layers;
filling the recesses with conductive layers to form a plurality of word lines;
forming pads having a generally island shape over the first vertical channel layers;
forming a common source line having a generally rectangular shape over the second vertical channel layers;
forming contact plugs over the pads; and
forming a bit line over the contact plugs;
wherein a width of the pad is greater than that of the first vertical channel layer and that of the contact plug.

### Claim 2 (depends on 1)

The method of claim 1, wherein the pads and the common source line are formed at substantially the same time.

### Claim 3 (depends on 1)

The method of claim 1, wherein the pads and the common source line include one of a polysilicon layer, a metal layer, and a stacked layer of a polysilicon layer and a metal layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein the pads and the first vertical channel layers have a relatively greater width than the contact plugs.

### Claim 5 (depends on 1)

The method of claim 1, wherein the common source line is in electrical contact with the second vertical channel layers.

### Claim 6 (depends on 1)

The method of claim 1, further comprising forming a conductive layer over the second vertical channel layers during the forming of the plurality of word lines.

### Claim 7 (depends on 6)

The method of claim 6, wherein the conductive layer formed over the second vertical channel layers is included in the common source line.

### Claim 8

A method of manufacturing a three-dimensional nonvolatile memory device, the method comprising:
depositing a plurality of interlayer insulating layers and a plurality of sacrificial layers in a stacked configuration along first vertical channel layers and second vertical channel layers, wherein the first and second vertical channel layers extend from a substrate;
etching portions of the plurality of the interlayer insulating layers and the plurality of sacrificial layers to form a slit, wherein portions of the sacrificial layers are exposed through a sidewall of the slit;
removing the portions of the sacrificial layers exposed by the slit to form recesses between the interlayer insulating layers;
forming word lines within the recesses;
forming a lower conductive layer of a common source line over the second vertical channel layers;
forming an insulating layer covering the lower conductive layer;
forming pads and an upper conductive layer of the common source line passing through the insulating layer, wherein the pads are formed over the first vertical channel layers and the upper conductive layer is formed over the lower conductive layer;
forming contact plugs over the pads; and
forming a bit line over the contact plugs.