# US 9,520,406 B2 · Method of making a vertical NAND device using sequential etching of multilayer stacks

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- Number: US 9,520,406 B2
- Document ID: US9520406B2
- Status: Granted
- Kind: B2
- Application number: 14/585,912
- Filed: 2014-12-30
- Published: 2015-04-30
- Granted: 2016-12-13
- Earliest claimed: 2013-03-12
- Assignees: SanDisk Technologies LLC
- Applicants: Sandisk Technologies Inc.
- Inventors: Raghuveer S. Makala; Yao-Sheng Lee; Jayavel Pachamuthu; Johann Alsmeier; Henry Chien
- Web page: https://patentgrep.com/patent/US9520406B2

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/00: EEPROM devices comprising charge-trapping gate insulators
- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors}
- H10D 30/689: {Vertical floating-gate IGFETs}
- H10D 30/693: {Vertical IGFETs having charge trapping gate insulators}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 88/01: {Manufacture or treatment}
- H10B 41/10: characterised by the top-view layout
- H10B 43/10: characterised by the top-view layout
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of making a vertical NAND device includes forming a lower portion of a memory stack over a substrate, forming a lower portion of memory openings in the lower portion of the memory stack, and at least partially filling the lower portion of the memory openings with a sacrificial material. The method also includes forming an upper portion of the memory stack over the lower portion of the memory stack and over the sacrificial material, forming an upper portion of the memory openings in the upper portion of the memory stack to expose the sacrificial material in the lower portion of the memory openings, removing the sacrificial material to connect the lower portion of the memory openings with a respective upper portion of the memory openings to form continuous memory openings, and forming a semiconductor channel in each continuous memory opening.

## Claims

### Claim 1

A method of making a vertical NAND device, comprising:
forming a lower portion of a memory stack over a substrate;
forming a lower portion of memory openings in the lower portion of the memory stack;
at least partially filling the lower portion of the memory openings with a sacrificial material;
forming an upper portion of the memory stack over the lower portion of the memory stack and over the sacrificial material;
forming an upper portion of the memory openings in the upper portion of the memory stack to expose the sacrificial material in the lower portion of the memory openings;
removing the sacrificial material to connect the lower portion of the memory openings with a respective upper portion of the memory openings to form continuous memory openings extending through the upper and the lower portions of the memory stack; and
forming a semiconductor channel in each continuous memory opening,
wherein at least partially filling the lower portion of the memory openings with the sacrificial material comprises forming a non-conformal sacrificial layer over the lower portion of the memory openings such that the sacrificial layer pinches off a top of the lower portion of the memory openings and leaves an air gap below it in the lower portion of the memory openings.

### Claim 2 (depends on 1)

The method of claim 1, wherein the lower and the upper portions of the memory stack comprise alternating insulating and sacrificial layers, and wherein the sacrificial material layers are removed and replaced with a memory film and control gate electrodes.

### Claim 3 (depends on 1)

The method of claim 1, wherein the lower and the upper portions of the memory stack comprise alternating insulating and control gate material layers.

### Claim 4 (depends on 3)

The method of claim 3, further comprising forming a memory film which comprises at least one charge storage region located between blocking and tunneling dielectric layers in each continuous memory opening prior to the step of forming the semiconductor channel.

### Claim 5 (depends on 4)

The method of claim 4, wherein:
the tunnel dielectric layer is located adjacent to the semiconductor channel;
the charge storage region is located adjacent to the tunnel dielectric layer;
the blocking dielectric layer is located adjacent to the charge storage region;
each control gate material layer comprises a control gate electrode which extends substantially parallel to a major surface of the substrate; and
the control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level.

### Claim 6 (depends on 5)

The method of claim 5, wherein the device comprises at least a 3×3 array of NAND strings, the first control gate electrode and the second control gate electrode are continuous in the array, and the first control gate electrode and the second control gate electrode do not have an air gap or a dielectric filled trench in the array.

### Claim 7 (depends on 5)

The method of claim 5, wherein:
each semiconductor channel has a pillar shape; and
the entire pillar-shaped semiconductor channel extends substantially perpendicularly to the major surface of the substrate.

### Claim 8 (depends on 1)

The method of claim 1, wherein the lower portion of the memory openings is formed by etching the lower portion of the memory stack using a first hard mask, and the upper portion of the memory openings is formed by etching the upper portion of the memory stack using at least one second hard mask.

### Claim 9 (depends on 8)

The method of claim 8, wherein etching the upper portion of the memory stack and removing the sacrificial material occur in a same etching step or in different etching steps.

### Claim 10 (depends on 1)

The method of claim 1, wherein at least partially filling the lower portion of the memory openings with a sacrificial material comprises completely filling the lower portion of the memory opening with a spin-on sacrificial carbon or polymer material.

### Claim 11 (depends on 1)

The method of claim 1, wherein:
forming the non-conformal sacrificial layer comprises forming a sacrificial silicon nitride layer by high pressure CVD over the entire lower portion of the memory stack and in the top of the lower portion of the memory openings, followed by planarization or etch-back to leave the sacrificial silicon nitride only in the top of the lower portion of the memory openings; and
removing the sacrificial material comprises either: (i) etching the silicon nitride during the step of forming the upper portion of the memory openings by etching the upper portion of the memory openings in the upper portion of the memory stack, or (ii) etching the silicon nitride using a hot phosphoric acid selective wet etch after the step of forming the upper portion of the memory openings.