# US 9,520,405 B2 · Semiconductor device

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- Number: US 9,520,405 B2
- Document ID: US9520405B2
- Status: Granted
- Kind: B2
- Application number: 14/505,180
- Filed: 2014-10-02
- Published: 2015-04-09
- Granted: 2016-12-13
- Earliest claimed: 2013-10-08
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Do-hyun Lee; Jae-duk Lee; Young-woo Park; Yung-hwan Son
- Inventors: Do-hyun Lee; Jae-duk Lee; Young-woo Park; Yung-hwan Son
- Web page: https://patentgrep.com/patent/US9520405B2

## CPC

- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10D 30/689: {Vertical floating-gate IGFETs}
- H10D 30/693: {Vertical IGFETs having charge trapping gate insulators}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device is provided. A channel layer is formed on a substrate. The channel layer is extended in a first direction substantially perpendicular to an upper surface of the substrate. A ground selection line is formed on a first region of the channel layer. A plurality of word lines is formed on a second region of the channel layer. A plurality of string selection lines is formed on a third region of the channel layer. The second region of the channel layer includes a first conductivity type dopant. The first, second and third regions of the channel layer are disposed along the first direction.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate;
a channel layer formed on the substrate and extended in a first direction substantially perpendicular to an upper surface of the substrate;
a ground selection line formed on a first region of the channel layer;
a plurality of word lines formed on a second region of the channel layer; and
a plurality of string selection lines formed on a third region of the channel layer,
wherein the second region of the channel layer comprises a first conductivity type dopant,
wherein the first, second and third regions of the channel layer are disposed along the first direction, and
wherein the third region of the channel layer comprises a second conductivity type dopant.

### Claim 2 (depends on 1)

The semiconductor device of claim 1,
wherein a sidewall of the second region of the channel region is aligned with a sidewall of the third region of the channel region.

### Claim 3 (depends on 1)

The semiconductor device of claim 1,
wherein the first region of the channel contact region comprises a second conductivity type dopant.

### Claim 4 (depends on 1)

The semiconductor device of claim 1,
wherein the first region of the channel region comprises a first type conductivity type dopant, and
wherein the first region of the channel region is in contact with the substrate.

### Claim 5 (depends on 1)

The semiconductor device of claim 1,
wherein the third region of the channel region comprises an n-type dopant.

### Claim 6 (depends on 5)

The semiconductor device of claim 5,
wherein the string selection line comprises at least two string selection lines.

### Claim 7 (depends on 1)

The semiconductor device of claim 1,
wherein the first conductivity type dopant is an n-type dopant including phosphorus, arsenic, or antimony.

### Claim 8 (depends on 1)

The semiconductor device of claim 1,
wherein the channel layer has an n-type dopant concentration in a range from about 5E16 atoms/cm3 to about 1E19 atoms/cm3.

### Claim 9

A semiconductor device comprising:
a substrate;
a ground selection transistor stacked on the substrate;
a plurality of memory cell transistors stacked on the ground selection transistor,
wherein the plurality of memory cell transistors is stacked on each other in a first direction,
wherein the first direction is substantially perpendicular to the substrate, wherein a lowermost memory cell transistor of the plurality of memory cell transistors is stacked on the ground selection transistor,
wherein the plurality of memory cell transistors comprises a first channel layer doped with a first impurity type dopant and extended in the first direction;
a string selection transistor stacked on an uppermost memory cell transistor of the plurality of memory cell transistors;
a drain electrode stacked on the string selection transistor in the first direction; and
a source region formed on the substrate, wherein the source region is spaced apart from the plurality of memory cell transistors in a second direction substantially perpendicular to the first direction,
wherein the string selection transistor comprises a second channel layer doped with a second conductivity type dopant and extended in the first direction.

### Claim 10 (depends on 9)

The semiconductor device of claim 9,
wherein the first impurity type dopant of the plurality of memory cell transistors is uniformly distributed in the first direction at a first concentration.

### Claim 11 (depends on 9)

The semiconductor device of claim 9,
wherein the second conductivity type dopant is uniformly distributed at a second concentration.

### Claim 12 (depends on 9)

The semiconductor device of claim 9, further comprising a lower dummy transistor and an upper dummy transistor, wherein the lower dummy transistor LDT is interposed between the ground selection transistor and the lowermost memory cell transistor, wherein the upper dummy transistor is interposed between the uppermost memory cell transistor and the string selection transistors.

### Claim 13 (depends on 9)

The semiconductor device of claim 9,
wherein the ground selection transistor comprises a third channel layer doped with a second conductivity type dopant,
wherein the first and second channel layers form an U-shaped channel layer, wherein a closed lower end of the U-shaped channel is in contact with the third channel layer.

### Claim 14 (depends on 9)

The semiconductor device of claim 9,
wherein the ground selection transistor comprises a third channel layer doped with a first conductivity type dopant,
wherein the first, second and third channel layers form an U-shaped channel layer, wherein a closed lower end of the U-shaped channel is in contact with the substrate.