# US 9,520,404 B2 · Asymmetric dense floating gate nonvolatile memory with decoupled capacitor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,520,404 B2 - Document ID: US9520404B2 - Status: Granted - Kind: B2 - Application number: 13/954,383 - Filed: 2013-07-30 - Published: 2015-02-05 - Granted: 2016-12-13 - Earliest claimed: 2013-07-30 - Assignees: Synopsys, Inc. - Applicants: Synopsys, Inc. - Inventors: Andrew E. Horch - Web page: https://patentgrep.com/patent/US9520404B2 ## CPC - H10B 41/70: the floating gate being an electrode shared by two or more components - H10B 41/10: characterised by the top-view layout - H10B 41/60: the control gate being a doped region, e.g. single-poly memory cell - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A nonvolatile memory (“NVM”) bitcell includes a capacitor, an asymmetrically doped transistor, and a tunneling device. The capacitor, transistor, and tunneling device are each electrically coupled to different active regions and metal contacts. The three devices are coupled by a floating gate that traverses the three active regions. The tunneling device is formed in a native region to allow for greater dynamic range in the voltage used to induce tunneling. The FN tunneling device is used to erase the device, allowing for faster page erasure, and thus allows for rapid testing and verification of functionality. The asymmetric transistor, in conjunction with the capacitor, is used to both program and read the logical state of the floating gate. The capacitor and floating gate are capacitively coupled together, removing the need for a separate selection device to perform read and write operations. ## Claims ### Claim 1 A non-volatile memory bitcell comprising: a tunneling device comprising a first portion of a floating gate above a first active region of a substrate, a portion of the first active region beneath the first portion of the floating gate, the first active region being a native region comprising a lightly doped drain (LDD) implant overlapping in the portion of the first active region beneath the first portion of the floating gate, and a first insulation layer between the portion of the first active region and the first portion of the floating gate, the tunneling device configured to cause charge carriers to transition between the first active region and the first portion of the floating gate responsive to a voltage being applied to the first active region; a transistor comprising a source, a drain, and a second portion of the floating gate above a second active region of the substrate, the source and drain formed in the second active region, wherein the source and the drain each comprise a first implant of a first polarity, wherein the source comprises a second implant of a second polarity opposite the first polarity, and wherein the drain does not include an implant of the second polarity; a capacitor comprising a first plate, a second plate, and a second insulation layer between the first and second plates, the first plate comprising a third portion of the floating gate above a third active region of the substrate, and the second plate comprising a portion of the third active region underneath the third portion of the floating gate. ### Claim 2 (depends on 1) The non-volatile memory bitcell of claim 1, wherein the tunneling device is a Fowler Nordheim (FN) tunneling device. ### Claim 3 (depends on 1) The non-volatile memory bitcell of claim 1, wherein electrons are transferred from the second active region to the second portion of the floating gate to program the bitcell responsive to applying a first set of voltages to the source of the transistor, the drain of the transistor, and the third active region. ### Claim 4 (depends on 3) The non-volatile memory bitcell of claim 3, wherein an amount of charge on the floating gate is read out responsive to applying a second set of voltages to the source of the transistor, the drain of the transistor, and the third active region. ### Claim 5 (depends on 1) The non-volatile memory bitcell of claim 1, wherein the first active region, the second active region, and the third active region are electrically isolated from each other. ### Claim 6 (depends on 5) The non-volatile memory bitcell of claim 5, wherein the first active region, the second active region, and the third active region are separated using shallow trench isolations. ### Claim 7 (depends on 1) The non-volatile memory bitcell of claim 1, wherein the first active region is a native region undoped from an original wafer prior to the deposition of the floating gate. ### Claim 8 (depends on 1) The non-volatile memory bitcell of claim 1, wherein the first active region comprises a charge carrier implant extending underneath the first portion of the floating gate. ### Claim 9 (depends on 1) The non-volatile memory bitcell of claim 1, wherein a width of the first portion of the floating gate over first active region is between 0.04 and 0.2 microns. ### Claim 10 (depends on 1) The non-volatile memory bitcell of claim 1, wherein the tunneling device is configured to prevent diode breakdown behavior in the first active region when the first active region is raised to 10 volts. ### Claim 11 (depends on 1) The non-volatile memory bitcell of claim 1, wherein the second active region comprises a well implant of charge carriers. ### Claim 12 (depends on 1) The non-volatile memory bitcell of claim 1, wherein the second implant of the source comprises a P-type halo implant and the first implant of the source comprises either a N-type lightly doped drain (LDD) implant or a source-drain (S/D) extension implant. ### Claim 13 (depends on 12) The non-volatile memory bitcell of claim 12, wherein the second implant of the source further comprises a P-type LDD implant. ### Claim 14 (depends on 1) The non-volatile memory bitcell of claim 1, wherein the first implant of the drain comprises a N-type LDD implant. ### Claim 15 (depends on 1) The non-volatile memory bitcell of claim 1, wherein the third active region is a native region undoped from an original wafer. ### Claim 16 (depends on 1) The non-volatile memory bitcell of claim 1, wherein the portion of floating gate above the third active region is rectangular. ### Claim 17 (depends on 1) The non-volatile memory bitcell of claim 1, wherein the third active region comprises a well implant of charge carriers. ### Claim 18 (depends on 1) The non-volatile memory bitcell of claim 1, wherein the portion of floating gate above the third active region is ring shaped. ### Claim 19 (depends on 1) The non-volatile memory bitcell of claim 1, wherein implant charge carriers extend underneath an entirety of the third portion of the floating gate. ### Claim 20 (depends on 1) The non-volatile memory bitcell of claim 1, wherein the third active region comprises a 5 volt N-type LDD implant. ### Claim 21 (depends on 1) The non-volatile memory bitcell of claim 1, wherein the first, second, and third portions of the floating gate are electrically coupled together. ### Claim 22 (depends on 1) The non-volatile memory bitcell of claim 1, wherein the third active region is shared with a plurality of other bitcells, and wherein the other bitcells share a metal contact. ### Claim 23 (depends on 1) The non-volatile memory bitcell of claim 1, wherein the first active region is shared with a plurality of other bitcells, and wherein the other bitcells share a metal contact. ### Claim 24 (depends on 1) The non-volatile memory bitcell of claim 1, wherein the bitcell is fabricated using a standard complementary metal oxide semiconductor (CMOS) logic process. ### Claim 25 (depends on 1) The non-volatile memory bitcell of claim 1, wherein the first active region is formed in a region of substrate with a dopant concentration of less than 1016 atoms/cm3. ### Claim 26 (depends on 1) The non-volatile memory bitcell of claim 1, wherein the third active region is formed in a region of substrate with a dopant concentration of less than 1016 atoms/cm3. ### Claim 27 (depends on 1) The non-volatile memory bitcell of claim 1, wherein the first active region is shared with another tunneling device of another bitcell. ### Claim 28 (depends on 1) The non-volatile memory bitcell of claim 1, wherein the third active region is shared with another capacitor of another bitcell. ### Claim 29 (depends on 1) The non-volatile memory bitcell of claim 1, wherein the first active region is formed by blocking well implants using a photoresist having, along a first axis, a first length that is greater than a second length along a second axis perpendicular to the first axis. ### Claim 30 (depends on 1) The non-volatile memory bitcell of claim 1, wherein the third active region is formed by blocking well implants using a photoresist having, along a first axis, a first length that is greater than a second length along a second axis perpendicular to the first axis. ### Claim 31 (depends on 1) The non-volatile memory bitcell of claim 1, wherein the first active region is enclosed by a larger non-active native region than the third active region. ### Claim 32 (depends on 1) The non-volatile memory bitcell of claim 1, wherein the first active region is formed in a region of substrate comprising a shallow well implant. ### Claim 33 (depends on 1) The non-volatile memory bitcell of claim 1, wherein the third active region is formed in a region of substrate comprising a shallow well implant. ### Claim 34 (depends on 1) The non-volatile memory bitcell of claim 1, wherein the first active region further comprises a VT adjustment implant having a same polarity as the LDD implant. ### Claim 35 (depends on 1) The non-volatile memory bitcell of claim 1, wherein the third active region comprises a LDD implant and a VT adjustment implant, both implants having a same polarity. ### Claim 36 A non-transitory machine readable medium comprising instructions that when executed cause a manufacturing facility to create a non-volatile memory bitcell that comprises: a tunneling device comprising: a first portion of a floating gate above a first active region of a substrate, a portion of the first active region beneath the first portion of the floating gate, the first active region being a native region comprising a lightly doped drain (LDD) implant overlapping in the portion of the first active region beneath the first portion of the floating gate, and a first insulation layer between the portion of the first active region and the first portion of the floating gate, the tunneling device configured to cause charge carriers to transition between the first active region and the first portion of the floating gate responsive to a voltage being applied to the first active region; a transistor comprising a source, a drain, and a second portion of the floating gate above a second active region of the substrate, the source and drain formed in the second active region, wherein the source and the drain each comprise a first implant of a first polarity, wherein the source comprises a second implant of a second polarity opposite the first polarity, and wherein the drain does not include an implant of the second polarity; and a capacitor comprising a first plate, a second plate, and a second insulation layer between the first and second plates, the first plate comprising a third portion of the floating gate above a third active region of the substrate, and the second plate comprising a portion of the third active region underneath the third portion of the floating gate.