# US 9,520,400 B2 · NOR structure flash memory and manufacturing method thereof

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- Number: US 9,520,400 B2
- Document ID: US9520400B2
- Status: Granted
- Kind: B2
- Application number: 14/398,849
- Filed: 2013-05-19
- Published: 2015-04-30
- Granted: 2016-12-13
- Earliest claimed: 2012-05-09
- Assignees: Csmc Technologies Fabi Co., Ltd.
- Applicants: Csmc Technologies Fab1 Co., Ltd.
- Inventors: Shizhen Sun; Hao Fang; Yong Gu
- Web page: https://patentgrep.com/patent/US9520400B2

## CPC

- H10D 30/0411: {of FETs having floating gates}
- H10B 41/00: Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B 41/30: characterised by the memory core region
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10D 30/681: {having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688)}
- H10D 30/6891: {characterised by the shapes, relative sizes or dispositions of the floating gate electrode}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10P 14/40: of conductive or resistive materials
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A NOR flash memory and its manufacturing method are provided in the present disclosure, they are in the field of flash memory. In the manufacturing method, a mask dielectric layer is formed on a second polysilicon layer of a gate stack structure. In addition, part of the mask dielectric layer is etched patternedly to expose part of the second polysilicon layer which is close to a source. Furthermore, the exposed second polysilicon layer is self aligned to form a metal silicide layer. Thus in the NOR flash memory, an unetched mask dielectric layer is substantially located between a metal silicide layer and a drain contacting hole of the NOR flash memory. A drain current between the gate electrode and the drain electrode is small, the above manufacturing method is not complex, a process window is large, a side effect is small, which are advantageous to large scale production.

## Claims

### Claim 1

A method of manufacturing a NOR flash memory having a substrate, comprising the following steps:
providing a gate stack structure configured to form the NOR flash memory, the gate stack structure comprising a tunneling dielectric layer, a first polysilicon layer, an inter-poly layer dielectric, a second polysilicon layer having a surface inclined at a non-zero angle relative to the first polysilicon layer, which are sequentially laminated from low to up;
forming a mask dielectric layer on the second polysilicon layer;
etching patternedly part of the mask dielectric layer to expose part of the second polysilicon layer which is close to a source of the NOR flash memory; and
self aligning the part of second polysilicon layer exposed during the etching to form a metal silicide layer;
wherein the entire top surface of the first polysilicon layer is horizontal relative to the substrate; and
wherein a portion of the top surface of the second polysilicon layer is inclined relative to the substrate.

### Claim 2 (depends on 1)

The method according to claim 1, wherein in the NOR flash memory, two symmetric flash memory units share a source to form a common source.

### Claim 3 (depends on 2)

The method according to claim 2, wherein part of the mask dielectric layer is etched when a corresponding dielectric layer on the common source of the NOR flash memory is etched.

### Claim 4 (depends on 3)

The method according to claim 3, wherein the thickness of the mask dielectric layer is in the range of from 30 nm to 100 nm.

### Claim 5 (depends on 3)

The method according to claim 3, wherein the etching is an anisotropic etching.

### Claim 6 (depends on 3)

The method according to claim 3, wherein the metal silicide is cobalt silicide or tungsten silicide.

### Claim 7 (depends on 1)

The method according to claim 1, wherein after the metal silicide layer is formed, the method further comprises:
forming a barrier layer of an interlayer dielectric;
forming an interlayer dielectric on the barrier layer;
flattening the interlayer dielectric; and
patterning to form a drain contacting hole leading out a drain electrode.

### Claim 8 (depends on 1)

The method according to claim 1, wherein the thickness of the mask dielectric layer is in the range of from 30 nm to 100 nm.

### Claim 9 (depends on 1)

The method according to claim 1, wherein the mask dielectric layer is made of silica.

### Claim 10 (depends on 1)

The method according to claim 1, wherein the etching is an anisotropic etching.

### Claim 11 (depends on 1)

The method according to claim 1, wherein the metal silicide is cobalt silicide or tungsten silicide.

### Claim 12 (depends on 1)

The method according to claim 1, wherein a 0.13 μm or less technology is used in the method.

### Claim 13 (depends on 1)

A NOR flash memory manufactured according to the method of claim 1, wherein the NOR flash memory comprises an unetched mask dielectric layer, the unetched mask dielectric layer is substantially located between a metal silicide layer and a drain contacting hole of the NOR flash memory.

### Claim 14 (depends on 13)

The NOR flash memory according to claim 13, wherein the thickness of the unetched mask dielectric layer is in the range of from 30 nm to 100 nm.

### Claim 15 (depends on 13)

The NOR flash memory according to claim 13, wherein a critical dimension of the NOR flash memory is 0.18 μm or less.

### Claim 16 (depends on 1)

The method of claim 1, wherein a portion of the top surface of the first polysilicon layer is horizontal, and a portion of the top surface of the second polysilicon layer directly above the first portion of the top surface of the first polysilicon layer is non-horizontal.