# US 9,520,399 B2 · Floating body memory cell having gates favoring different conductivity type regions

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- Number: US 9,520,399 B2
- Document ID: US9520399B2
- Status: Granted
- Kind: B2
- Application number: 15/209,622
- Filed: 2016-07-13
- Published: 2016-11-03
- Granted: 2016-12-13
- Earliest claimed: 2006-12-22
- Assignees: Intel Corporation
- Applicants: Peter L. D. Chang; Uygar E. Avci; David Kencke; Ibrahim Ban
- Inventors: Peter L. D. Chang; Uygar E. Avci; David Kencke; Ibrahim Ban
- Web page: https://patentgrep.com/patent/US9520399B2

## CPC

- H10B 12/20: {DRAM devices comprising floating-body transistors, e.g. floating-body cells}
- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10B 12/01: {Manufacture or treatment}
- H10B 12/36: {the transistor being a FinFET}
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6215: {having multiple independently-addressable gate electrodes}
- H10D 30/711: {having floating bodies}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/013: {of electrodes having a conductor capacitively coupled to a semiconductor by an insulator}
- H10D 64/665: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671)}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/68: characterised by the insulator, e.g. by the gate insulator
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0181: {Manufacturing their gate insulating layers}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/0191: {Manufacturing their doped wells}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/853: {comprising FinFETs}
- H10D 84/859: {comprising both N-type and P-type wells, e.g. twin-tub}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10B 12/056: {the transistor being a FinFET}
- Y10S 257/903: FET configuration adapted for use as static memory cell
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

## Claims

### Claim 1

A semiconductor structure, comprising:
a semiconductor substrate comprising a P well region having a first semiconductor fin protruding therefrom and an N well region having a second semiconductor fin protruding therefrom, the first semiconductor fin spaced apart from the second semiconductor fin, wherein the P well region is directly adjacent to the N well region in the semiconductor substrate;
a trench isolation layer disposed on the semiconductor substrate between the first and second semiconductor fins, wherein the first and second semiconductor fins extend above the trench isolation layer;
a gate dielectric layer disposed on the first and second semiconductor fins and on the trench isolation layer, wherein the gate dielectric layer is continuous between the first and second semiconductor fins;
an n type metal gate layer disposed over the gate dielectric layer over the first semiconductor fin but not over the second semiconductor fin, wherein the n type metal gate layer is further disposed on a portion of but not all of the trench isolation layer; and
a p type metal gate layer disposed over the gate dielectric layer over the second semiconductor fin, wherein the p type metal gate layer is further disposed over the trench isolation layer and over the n type metal gate layer.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the p type metal gate layer comprises titanium nitride.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein the n type metal gate layer comprises titanium.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein the p type metal gate layer has a work function in the range of 4.6 to 5.2 eV.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein the n type metal gate layer has a work function in the range of 3.9 to 4.6 eV.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, wherein the gate dielectric layer comprises HfO2.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, wherein the p type metal gate layer comprises titanium nitride, the n type metal gate layer comprises titanium, and the gate dielectric layer comprises HfO2.

### Claim 8 (depends on 1)

The semiconductor structure of claim 1, wherein the semiconductor substrate is a bulk silicon semiconductor substrate.

### Claim 9

A method of fabricating a semiconductor structure, the method comprising:
forming a P well region and an N well region in a semiconductor substrate, wherein the P well region is directly adjacent to the N well region;
forming a first semiconductor fin in the P well region and forming a second semiconductor fin in the N well region, the first semiconductor fin spaced apart from the second semiconductor fin;
forming a trench isolation layer on the semiconductor substrate between the first and second semiconductor fins, wherein the first and second semiconductor fins extend above the trench isolation layer;
forming a gate dielectric layer on the first and second semiconductor fins and on the trench isolation layer, wherein the gate dielectric layer is continuous between the first and second semiconductor fins;
forming an n type metal layer over the gate dielectric layer;
patterning the n type metal layer to form an n type metal gate layer over the gate dielectric layer over the first semiconductor fin but not over the second semiconductor fin, wherein the n type metal gate layer is further formed on a portion of but not all of the trench isolation layer; and
forming a p type metal gate layer over the gate dielectric layer over the second semiconductor fin, wherein the p type metal gate layer is further formed over the trench isolation layer and over the n type metal gate layer.

### Claim 10 (depends on 9)

The method of claim 9, wherein the p type metal gate layer comprises titanium nitride.

### Claim 11 (depends on 9)

The method of claim 9, wherein the n type metal gate layer comprises titanium.

### Claim 12 (depends on 9)

The method of claim 9, wherein the p type metal gate layer has a work function in the range of 4.6 to 5.2 eV.

### Claim 13 (depends on 9)

The method of claim 9, wherein the n type metal gate layer has a work function in the range of 3.9 to 4.6 eV.

### Claim 14 (depends on 9)

The method of claim 9, wherein the gate dielectric layer comprises HfO2.

### Claim 15 (depends on 9)

The method of claim 9, wherein the p type metal gate layer comprises titanium nitride, the n type metal gate layer comprises titanium, and the gate dielectric layer comprises HfO2.

### Claim 16 (depends on 9)

The method of claim 9, wherein the semiconductor substrate is a bulk silicon semiconductor substrate.