# US 9,520,397 B2 · Abrupt source/drain junction formation using a diffusion facilitation layer

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- Number: US 9,520,397 B2
- Document ID: US9520397B2
- Status: Granted
- Kind: B2
- Application number: 14/697,024
- Filed: 2015-04-27
- Published: 2015-09-24
- Granted: 2016-12-13
- Earliest claimed: 2014-03-21
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Kangguo Cheng; Bruce B. Doris; Pouya Hashemi; Ali Khakifirooz; Alexander Reznicek
- Web page: https://patentgrep.com/patent/US9520397B2

## CPC

- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 62/834: further characterised by the dopants
- H10D 64/259: {Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/835: {comprising LDMOS}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10P 32/1408: {from or through or into an external applied layer, e.g. photoresist or nitride layers}
- H10P 32/171: {being group IV material}
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of forming a field effect transistor (FET) device includes forming a diffusion facilitation layer on top of a semiconductor substrate; forming a doped, raised source/drain (RSD) layer on the diffusion facilitation layer; removing a portion of the diffusion facilitation layer, corresponding to a region directly above a channel region of the FET device; and performing an anneal so as to define abrupt source and drain junctions in the semiconductor substrate, wherein dopant atoms from the doped RSD layer diffuse within the diffusion facilitation layer at a faster rate than with respect to the semiconductor substrate.

## Claims

### Claim 1

A field effect transistor (FET) device, comprising:
a diffusion facilitation layer comprising silicon germanium formed on top of a silicon semiconductor substrate;
a doped, raised source/drain (RSD) layer formed on the diffusion facilitation layer, wherein the RSD layer is doped with one or more of arsenic and phosphorous;
the diffusion facilitation layer having a portion thereof removed, corresponding to a region directly above a channel region of the FET device; and
abrupt source and drain junctions defined in the semiconductor substrate, wherein the diffusion facilitation layer and the semiconductor substrate comprise materials such that dopant atoms from the doped RSD layer diffuse within the diffusion facilitation layer at a faster rate than with respect to the semiconductor substrate.

### Claim 2 (depends on 1)

The device of claim 1, wherein the diffusion facilitation layer is epitaxially grown on the semiconductor substrate.

### Claim 3 (depends on 2)

The device of claim 2, wherein the diffusion facilitation layer has a thickness of about 3 to about 25 nanometers (nm).

### Claim 4 (depends on 3)

The device of claim 3, wherein the source and drain junctions extend about 3-5 nm below a top surface of the semiconductor substrate.

### Claim 5

A field effect transistor (FET) device, comprising:
a diffusion facilitation layer comprising silicon formed on top of a silicon germanium semiconductor substrate;
a doped, raised source/drain (RSD) layer formed on the diffusion facilitation layer, wherein the RSD layer is doped with boron;
the diffusion facilitation layer having a portion thereof removed, corresponding to a region directly above a channel region of the FET device; and
abrupt source and drain junctions defined in the semiconductor substrate, wherein the diffusion facilitation layer and the semiconductor substrate comprise materials such that dopant atoms from the doped RSD layer diffuse within the diffusion facilitation layer at a faster rate than with respect to the semiconductor substrate.

### Claim 6 (depends on 5)

The device of claim 5, wherein the diffusion facilitation layer is epitaxially grown on the semiconductor substrate.

### Claim 7 (depends on 6)

The device of claim 6, wherein the diffusion facilitation layer has a thickness of about 3 to about 25 nanometers (nm).

### Claim 8 (depends on 7)

The device of claim 7, wherein the source and drain junctions extend about 3-5 nm below a top surface of the semiconductor substrate.