# US 9,520,396 B2 · Method for making high voltage integrated circuit devices in a fin-type process and resulting devices

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- Number: US 9,520,396 B2
- Document ID: US9520396B2
- Status: Granted
- Kind: B2
- Application number: 14/965,193
- Filed: 2015-12-10
- Published: 2016-04-21
- Granted: 2016-12-13
- Earliest claimed: 2014-10-15
- Assignees: Globalfoundries Inc.
- Applicants: GLOBALFOUNDRIES Inc.
- Inventors: Jagar Singh
- Web page: https://patentgrep.com/patent/US9520396B2

## CPC

- H10D 84/834: {comprising FinFETs}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6212: {having fin-shaped semiconductor bodies having non-rectangular cross-sections}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/124: {Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Methods for making high voltage IC devices utilizing a fin-type process and resulting devices are disclosed. Embodiments include forming two pluralities of silicon fins on a substrate layer, separated by a space, wherein adjacent silicon fins are separated by a trench; forming an oxide layer on the substrate layer and filling a portion of each trench; forming two deep isolation trenches into the oxide layer and the substrate layer adjacent to the two pluralities of silicon fins; forming a graded voltage junction by implanting a dopant into the substrate layer below the two pluralities of silicon fins; forming a gate structure on the oxide layer and between the two pluralities of silicon fins; implanting a dopant into and under the two pluralities of silicon fins, forming source and drain regions; and forming an epitaxial layer onto the two pluralities of silicon fins to form merged source and drain fins.

## Claims

### Claim 1

A device comprising:
first and second pluralities of silicon fins on an upper surface of a substrate layer, separated by a space, wherein each pair of adjacent silicon fins is separated by a trench along the upper surface of the substrate layer;
an oxide layer on the upper surface of the substrate layer filling in a portion of each trench along the upper surface of the substrate layer;
first and second deep isolation trenches in the oxide layer and in the substrate layer adjacent to the first and second pluralities of silicon fins;
a graded voltage junction comprising one or more concentration levels of a dopant in the substrate layer below each of the first and second pluralities of silicon fins;
a gate structure on an upper surface of the oxide layer, positioned at the space between the first and second pluralities of silicon fins;
source and drain regions implanted by a dopant in and under the first and second pluralities of silicon fins; and
an epitaxial layer on the first and second pluralities of silicon fins forming merged source and drain fins, respectively.

### Claim 2 (depends on 1)

The device of claim 1, further comprises:
a high voltage junction comprising a graded junction and a high concentration level of the dopant in the substrate layer below each of the first and second pluralities of silicon fins forming a high voltage source region and a high voltage drain region.

### Claim 3 (depends on 1)

The device of claim 1, further comprises:
a low voltage junction comprising a high concentration level of the dopant in a second source region and a second drain region in the substrate layer forming a low voltage source region and a low voltage drain region.

### Claim 4 (depends on 1)

The device of claim 1, further comprising:
a layer of N-epitaxial or embedded silicon-germanium on exposed surfaces of the first and second pluralities of silicon fins.

### Claim 5 (depends on 1)

The device of claim 1, further comprising:
a deep gate isolation trench substantially under the gate structure and in between the one or more source regions and the one or more drain regions.

### Claim 6 (depends on 1)

The device of claim 1, further comprising:
a deep isolation trench adjacent to an inner boundary of the drain region.

### Claim 7 (depends on 1)

The device of claim 1, further comprising:
the first and second pluralities of silicon fins oriented in parallel with the gate structure.

### Claim 8 (depends on 1)

The device of claim 1, further comprising:
the first and second pluralities of silicon fins oriented perpendicular to the gate structure.

### Claim 9

A device comprising:
first and second pluralities of silicon fins on an upper surface of a substrate layer, separated by a space, wherein each pair of adjacent silicon fins is separated by a trench along the upper surface of the substrate layer;
an oxide layer on the upper surface of the substrate layer and filling in a portion of each trench along the upper surface of the substrate layer;
first and second deep isolation trenches in the oxide layer and in the substrate layer adjacent to the first and second pluralities of silicon fins; and
a graded voltage junction comprising one or more concentration levels of a dopant into the substrate layer below each of the first and second pluralities of silicon fins.

### Claim 10 (depends on 9)

The device of claim 9, further comprising: a gate structure on an upper surface of the oxide layer, positioned at the space between the first and second pluralities of silicon fins.

### Claim 11 (depends on 10)

The device of claim 10, further comprising:
one or more first source and first drain regions implanted by a dopant in and under the first and second pluralities of silicon fins; and
an epitaxial layer on the first and second pluralities of silicon fins forming merged source and drain fins, respectively.

### Claim 12 (depends on 9)

The device of claim 9, further comprising:
a high voltage junction comprising a graded junction and a high concentration level of the dopant in the substrate layer below each of the first and second pluralities of silicon fins forming a high voltage source region and a high voltage drain region.

### Claim 13 (depends on 11)

The device of claim 11, further comprising:
a low voltage junction comprising a high concentration level of the dopant in a second source region and a second drain region in the substrate layer forming a low voltage source region and a low voltage drain region.

### Claim 14 (depends on 9)

The device of claim 9, further comprising:
a layer of N-epitaxial or embedded silicon-germanium on exposed surfaces of the first and second pluralities of silicon fins.

### Claim 15 (depends on 11)

The device of claim 11, further comprising:
a deep gate isolation trench substantially under the gate structure and in between the one or more first source regions and the one or more first drain regions.

### Claim 16 (depends on 11)

The device of claim 11, further comprising:
a deep isolation trench adjacent to an inner boundary of the one or more first drain regions.

### Claim 17 (depends on 10)

The device of claim 10, further comprising:
the first and second pluralities of silicon fins oriented in parallel with the gate structure.

### Claim 18 (depends on 10)

The device of claim 10, further comprising:
the first and second pluralities of silicon fins oriented perpendicular to the gate structure.