# US 9,520,395 B2 · FinFET devices comprising a dielectric layer/CMP stop layer/hardmask/etch stop layer/gap-fill material stack

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 9,520,395 B2
- Document ID: US9520395B2
- Status: Granted
- Kind: B2
- Application number: 14/949,481
- Filed: 2015-11-23
- Published: 2016-03-17
- Granted: 2016-12-13
- Earliest claimed: 2014-04-22
- Assignees: Globalfoundries Inc.
- Applicants: Globalfoundries Inc.
- Inventors: Guillaume Bouche; Andy Wei; Xiang Hu; Jerome F. Wandell; Sandeep Gaan
- Web page: https://patentgrep.com/patent/US9520395B2

## CPC

- H10D 84/834: {comprising FinFETs}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10P 14/3238: {being insulating materials}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Provided are approaches for patterning multiple, dense features in a semiconductor device using a memorization layer. Specifically, an approach includes: patterning a plurality of openings in a memorization layer; forming a gap-fill material within each of the plurality of openings; removing the memorization layer; removing an etch stop layer adjacent the gap-fill material, wherein a portion of the etch stop layer remains beneath the gap-fill material; etching a hardmask to form a set of openings above the set of gate structures, wherein the etch to the hardmask also removes the gap-fill material from atop the remaining portion of the etch stop layer; and etching the semiconductor device to remove the hardmask within each of the set of openings. In one embodiment, a set of dummy S/D contact pillars is then formed over a set of fins of the semiconductor device by etching a dielectric layer selective to the gate structures.

## Claims

### Claim 1

A semiconductor device comprising:
a set of gate structures over a set of fins within a substrate;
a set of layers formed over the set of gate structures, the set of layers including a dielectric layer over the set of gate structures, a chemical mechanical planarization stop layer (CMPSL) over the dielectric layer, and a hardmask over the CMPSL; and
an etch stop layer and a gap-fill material formed over the hardmask in an area of the semiconductor device above the set of fins and adjacent to each of the set of gate structures.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, the gap-fill material material comprising at least one of: a-C, silicon oxycarbide (SiOC), silicon nitride (SiN), organic planarization layer (OPL), titanium nitride (TiN), high-density plasma (HDP) nitride, deep ultraviolet light absorbing oxide (DUO), and flowable chemical vapor deposition (FCVD) oxide.

### Claim 3 (depends on 1)

The method according to claim 1, the dielectric layer comprising a TEOS layer, the CMPSL comprising nitride, and the etch stop layer comprising silicon oxynitride.

### Claim 4 (depends on 1)

The method according to claim 1, the hardmask comprising an amorphous-carbon (a-C) layer.

### Claim 5

A semiconductor device comprising:
a set of gate structures over a set of fins within a substrate;
an oxide material formed between each pair of adjacent gate structures of the set of gate structures; and
a set of dummy source/drain (S/D) contact pillars formed over the oxide material, wherein the set of dummy S/D contact pillars comprises tetra ethyl ortho silicate (TEOS).

### Claim 6 (depends on 5)

The semiconductor device of claim 5, further comprising a gate capping layer over each of the set of gate structures.

### Claim 7 (depends on 5)

The semiconductor device of claim 5, wherein the set of dummy S/D contact pillars further comprises a chemical mechanical planarization stop layer (CMPSL).

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the CMPSL comprises nitride.