# US 9,520,394 B1 · Contact structure and extension formation for III-V nFET

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- Number: US 9,520,394 B1
- Document ID: US9520394B1
- Status: Granted
- Kind: B1
- Application number: 14/718,425
- Filed: 2015-05-21
- Published: 2016-11-24
- Granted: 2016-12-13
- Earliest claimed: 2015-05-21
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Veeraraghavan S. Basker; Alexander Reznicek
- Web page: https://patentgrep.com/patent/US9520394B1

## CPC

- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/01: Manufacture or treatment
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 30/751: {having composition variations in the channel regions}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/113: {Isolations within a component, i.e. internal isolations}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/82: Heterojunctions
- H10D 62/85: being Group III-V materials, e.g. GaAs
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/02: characterised by using material-based technologies
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/05: using Group III-V technology
- H10D 84/08: using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
- H10D 84/834: {comprising FinFETs}
- H10D 84/853: {comprising FinFETs}
- H10D 86/011: {comprising FinFETs}
- H10D 86/215: {comprising FinFETs}
- H10P 14/2905: {Silicon, silicon germanium or germanium}
- H10P 14/2924: {Structures}
- H10P 14/3218: {Phosphides}
- H10P 14/3221: {Arsenides}
- H10P 14/3248: {consisting of two layers}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3421: {Arsenides}
- H10P 14/3802: {Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth}
- H10P 14/3822: {Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10P 30/28: characterised by an annealing step, e.g. for activation of dopants
- H10P 32/14: within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
- H10P 32/174: {being Group III-V material}
- H10P 95/408: {of Group III-V semiconductors, e.g. to render them semi-insulating}
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10P 95/904: {of Group III-V semiconductors}
- H10P 14/24: using chemical vapour deposition [CVD]
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

FinFET devices including III-V fin structures and silicon-based source/drain regions are formed on a semiconductor substrate. Silicon is diffused into the III-V fin structures to form n-type junctions. Leakage through the substrate is addressed by forming p-n junctions adjoining the source/drain regions and isolating the III-V fin structures under the channel regions.

## Claims

### Claim 1

A structure comprising:
a semiconductor substrate;
a plurality of columns extending from the semiconductor substrate, the columns being separated by a plurality of recesses, each of the columns including a III-V base and a III-V fin structure, the III-V fin structure comprising arsenic and being positioned on the III-V base;
a silicon-containing layer adjoining the semiconductor substrate, the silicon-containing layer comprising a plurality of n-type source/drain regions, and
a plurality of n-type junctions adjoining the source/drain regions, each of the junctions including silicon diffused within the III-V fin structures and arsenic diffused within the source/drain regions, wherein the silicon-containing layer includes a p-type region adjoining the n-type source/drain regions, forming a plurality of p-n junctions therewith.

### Claim 2 (depends on 1)

The structure of claim 1, wherein the III-V base of each column includes a semi-isolating III-V layer adjoining one of the III-V fin structures.

### Claim 3 (depends on 2)

The structure of claim 2, wherein each column further includes a gate structure adjoining one of the III-V fin structures.

### Claim 4 (depends on 3)

The structure of claim 3, wherein the semiconductor substrate includes a monocrystalline silicon-containing portion, the p-type region directly contacting the monocrystalline silicon-containing portion of the semiconductor substrate.

### Claim 5 (depends on 4)

The structure of claim 4, wherein the monocrystalline silicon-containing portion of the semiconductor substrate consists essentially of silicon or silicon germanium.

### Claim 6 (depends on 4)

The structure of claim 4, further including spacers on the gate structures.

### Claim 7 (depends on 1)

The structure of claim 1, wherein the semiconductor substrate includes a monocrystalline semiconducting surface portion selected from the group consisting of silicon, silicon germanium, and germanium, the silicon-containing layer adjoining the surface portion of the semiconductor substrate.

### Claim 8 (depends on 2)

The structure of claim 2, wherein the semi-isolating III-V layer is formed from InAlAs and the III-V fin structures are formed from In0.53Ga0.47As.

### Claim 9 (depends on 1)

The structure of claim 1, wherein each column further includes a gate structure adjoining one of the III-V fin structures.

### Claim 10 (depends on 9)

The structure of claim 9, wherein the semiconductor substrate includes a monocrystalline silicon-containing portion, the p-type region directly contacting the monocrystalline silicon-containing portion of the semiconductor substrate.

### Claim 11 (depends on 10)

The structure of claim 10, wherein the monocrystalline silicon-containing portion of the semiconductor substrate consists essentially of silicon or silicon germanium.

### Claim 12 (depends on 10)

The structure of claim 10, further including spacers on the gate structures.