# US 9,520,393 B2 · Fully substrate-isolated FinFET transistor

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- Number: US 9,520,393 B2
- Document ID: US9520393B2
- Status: Granted
- Kind: B2
- Application number: 14/587,872
- Filed: 2014-12-31
- Published: 2015-04-23
- Granted: 2016-12-13
- Earliest claimed: 2012-12-21
- Assignees: STMicroelectronics S.r.l.
- Applicants: Stmicroelectronics, Inc.
- Inventors: Nicolas Loubet; Prasanna Khare
- Web page: https://patentgrep.com/patent/US9520393B2

## CPC

- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/66: Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/834: {comprising FinFETs}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3602: {In-situ cleaning}
- H10P 50/242: {of Group IV materials}
- H10P 50/691: {for Group IV materials or Group III-V materials}
- H10P 95/062: {involving a dielectric removal step}
- H10W 10/011: {of isolation regions comprising dielectric materials}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/10: Isolation regions comprising dielectric materials
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Channel-to-substrate leakage in a FinFET device can be prevented by inserting an insulating layer between the semiconducting channel and the substrate. Similarly, source/drain-to-substrate leakage in a FinFET device can be prevented by isolating the source/drain regions from the substrate by inserting an insulating layer between the source/drain regions and the substrate. The insulating layer isolates the conduction path from the substrate both physically and electrically, thus preventing current leakage. If an array of semiconducting fins is made up of a multi-layer stack, the bottom material can be removed thus yielding a fin array that is suspended above the silicon surface. A resulting gap underneath the remaining top fin material can then be filled in with oxide to better support the fins and to isolate the array of fins from the substrate. The resulting FinFET device is fully substrate-isolated in both the gate region and the source/drain regions.

## Claims

### Claim 1

A FinFET transistor, comprising:
an array of conductive fin channels suspended over a silicon substrate and spaced apart from the silicon substrate by an insulating layer;
a-doped epitaxial layer in contact with portions of the array of conductive fin channels, the doped epitaxial layer suspended over the silicon substrate and spaced apart from the silicon substrate by the insulating layer;
a conformal gate overlying the array of conductive fin channels, the conformal gate operable to control current flow within the conductive fin channels in response to an applied voltage; and
a pair of insulating trenches aligned substantially parallel to the conductive fin channels.

### Claim 2 (depends on 1)

The FinFET transistor of claim 1 wherein the conformal gate comprises a dielectric layer having a dielectric constant greater than 4.0, and a bulk gate material that includes a metal.

### Claim 3 (depends on 1)

The FinFET transistor of claim 1, further comprising one or more of well implants and pocket implants within the silicon substrate.

### Claim 4 (depends on 1)

The FinFET transistor of claim 1 wherein the array of conductive fin channels includes an epitaxially grown silicon material.

### Claim 5 (depends on 1)

The FinFET transistor of claim 1 wherein the insulating layer is an oxide.

### Claim 6 (depends on 1)

The FinFET transistor of claim 1 wherein the doped epitaxial layer is in contact with portions of the array of conductive fin channels outside the conformal gate.

### Claim 7

A device comprising:
an array of raised fin structures of a FinFET transistors formed of a first semiconductor material, the fin structures being suspended over a semiconductor substrate of a bulk silicon wafer material, and the fin structures being vertically separated from the semiconductor substrate by at least one insulating material along a previously-etched bottom surface of the fin structures;
a doped epitaxial layer in contact with the fin structures at source/drain regions of the fin structures, the doped epitaxial layer being suspended over the semiconductor substrate and vertically separated from the semiconductor substrate by the at least one insulating material; and
a conformal gate electrode overlying channel regions of the fin structures, the conformal gate electrode being adjacent the doped epitaxial layer.

### Claim 8 (depends on 7)

The device of claim 7 wherein the first semiconductor material comprises an epitaxially grown silicon material.

### Claim 9

A device comprising:
an array of raised fin structures of a FinFET transistors formed of a first semiconductor material, the structures being suspended over a semiconductor substrate of a bulk silicon wafer material, and the fin structures being vertically separated from the semiconductor substrate by at least one insulating material along a previously-etched bottom surface of the fin structures;
a doped epitaxial layer in contact with the fin structures at source/drain regions of the fin structures, the doped epitaxial layer being suspended over the semiconductor substrate and vertically separated from the semiconductor substrate by the at least one insulating material; and
a conformal gate electrode overlying channel regions of the fin structures, the conformal gate electrode being adjacent the doped epitaxial layer,
at least at the channel region of at least one of the fin structures, the first semiconductor material having a larger lattice structure in at least one direction than a second semiconductor material of the semiconductor substrate at a portion located below the channel region of the at least one of the fin structures.

### Claim 10 (depends on 9)

The device of claim 9 wherein a first dimension of at least one of the fin structures at the channel region is 22 nm or smaller.

### Claim 11 (depends on 7)

The device of claim 7 wherein the gate electrode comprises a metal material.

### Claim 12 (depends on 7)

The device of claim 7 wherein the at least one insulating material comprises an oxide material.

### Claim 13

A device comprising:
an array of raised fin structures formed of a first semiconductor material, the raised fin structures being suspended over a semiconductor substrate of a second semiconductor material and being vertically separated from the semiconductor substrate by an insulating region in direct contact with bottom surfaces of the raised fin structures, each raised fin structure including an impurity-doped source region, an impurity-doped drain region, and a channel region extending between the impurity-doped source and drain regions; and
a conformal gate electrode overlying the channel regions of the raised fin structures, the conformal gate electrode being adjacent to the impurity-doped source and drain regions.

### Claim 14 (depends on 13)

The device of claim 13 wherein the semiconductor substrate is a bulk silicon wafer.

### Claim 15 (depends on 13)

The device of claim 13 wherein the impurity-doped source and drain regions include doped epitaxial layers suspended over the semiconductor substrate and vertically separated from the semiconductor substrate by the at least one insulating region, and wherein the gate electrode is adjacent to the doped epitaxial layers of the impurity-doped source and drain regions.

### Claim 16 (depends on 13)

The device of claim 13 wherein the first semiconductor material comprises an epitaxially grown silicon material.

### Claim 17

A device comprising:
an array of raised fin structures formed of a first semiconductor material, the raised fin structures being suspended over a semiconductor substrate of a second semiconductor material and being vertically separated from the semiconductor substrate by an insulating region in direct contact with bottom surfaces of the raised fin structures, each raised fin structure including an impurity-doped source region, an impurity-doped drain region, and a channel region extending between the impurity-doped source and drain regions; and
a conformal gate electrode overlying the channel regions of the raised fin structures, the conformal gate electrode being adjacent to the impurity-doped source and drain regions,
at the channel region of at least one of the raised fin structures, the first semiconductor material having a larger lattice structure in at least one direction than a corresponding portion of the semiconductor substrate located below the channel region.

### Claim 18 (depends on 17)

The device of claim 17 wherein the second semiconductor material comprises a silicon material.

### Claim 19 (depends on 13)

The device of claim 13 wherein a first dimension of at least one of the raised fin structures at the channel region is 22 nm or smaller.

### Claim 20 (depends on 13)

The device of claim 13 wherein the gate electrode comprises a metal material.

### Claim 21 (depends on 13)

The device of claim 13 wherein the insulating region comprises an oxide material.