# US 9,520,392 B1 · Semiconductor device including finFET and fin varactor

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- Number: US 9,520,392 B1
- Document ID: US9520392B1
- Status: Granted
- Kind: B1
- Application number: 14/954,050
- Filed: 2015-11-30
- Granted: 2016-12-13
- Earliest claimed: 2015-11-30
- Assignees: International Business Machines Corporation; Globalfoundries Inc.
- Applicants: International Business Machines Corporation; GlobalFoundries, Inc.
- Inventors: Kangguo Cheng; Junli Wang; Ruilong Xie; Tenko Yamashita
- Web page: https://patentgrep.com/patent/US9520392B1

## CPC

- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D 1/045: {of capacitors having potential barriers, e.g. varactors}
- H10D 1/64: Variable-capacitance diodes, e.g. varactors
- H10D 30/0217: {forming self-aligned punch-through stoppers or threshold implants under gate regions}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/813: {Combinations of field-effect devices and capacitor only}
- H10P 50/693: {characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane}
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a semiconductor substrate having a fin-type field effect transistor (finFET) on a first region and a fin varactor on a second region. The finFET includes a first semiconductor fin that extends from an upper finFET surface thereof to the upper surface of the first region to define a first total fin height. The fin varactor includes a second semiconductor fin that extends from an upper varactor surface thereof to the upper surface of the second region to define a second total fin height that is different from the first total fin height of the finFET.

## Claims

### Claim 1

A method of forming a semiconductor device comprising:
forming a first fin corresponding to a field effect transistor (FET) on a first region of a semiconductor substrate and forming a second fin corresponding to a varactor on a second region of the semiconductor substrate;
recessing the first region with respect to the second region so as to increase a physical height of the first fin with respect to a physical height of the second fin; and
doping the first fin and the second fin so as to form a finFET in the first region and a fin varactor in the second region,
wherein recessing the first region further comprises:
depositing a masking layer atop the first and second regions so as to cover the first fin and the second fin, and selectively patterning the masking layer to expose the first region while maintaining coverage of the second region;
depositing a conformal spacer layer atop the first region and the second region, the conformal spacer layer covering sidewalls and an upper surface of the first fin and an upper masking surface of the masking layer;
performing a first etching process selective to the conformal spacer layer so as to expose the semiconductor substrate of the first region; and
performing a second etching process selective to the semiconductor substrate so as to recess the first region with respect to the second region.

### Claim 2 (depends on 1)

The method of claim 1, wherein the doping includes doping a first fin portion of the first fin with respect to the second fin.

### Claim 3 (depends on 2)

The method of claim 2, wherein the first etching process includes forming spacers on sidewalls of the first fin, and selectively doping the first fin portion includes inhibiting doping implantation in a covered portion of the first fin covered by the spacers while implanting dopants in the first fin portion.

### Claim 4 (depends on 1)

The method of claim 1, wherein doping the first fin and the second fin forms a doped punchthrough stop (PTS) layer beneath each the first semiconductor fin and the second semiconductor fin.

### Claim 5

A method of forming a semiconductor device comprising:
patterning a semiconductor substrate including a first region and a second region so as to form a plurality of semiconductor fins;
recessing the first region with respect to a second region so as to form a first semiconductor fin in the first region having a first total height and a second semiconductor fin in the second region having a second total height that is less than the first total height; and
doping a first fin portion of the first semiconductor fin to form a finFET and entirely doping the second semiconductor fin to form a fin varactor,
wherein recessing the first region further comprises:
depositing a masking layer atop the first and second regions so as to cover the first semiconductor fin and the second semiconductor fin, and selectively patterning the masking layer to expose the first region while maintaining coverage of the second region;
depositing a conformal spacer layer that covers first sidewalls and an upper surface of the first semiconductor fin and second sidewalls and an upper masking surface of the masking layer;
performing a first etching process selective to the conformal spacer layer so as to expose the semiconductor substrate of the first region; and
performing a second etching process selective to the semiconductor substrate so as to recess the first region with respect to the second region.

### Claim 6 (depends on 5)

The method of claim 5, wherein doping the first portion comprises:
forming spacers on the first sidewalls located between the upper surface and the first fin portion in response to the first etching process;
implanting dopants in the first fin portion; and
blocking dopants using the spacers so as to form a self-aligned un-doped channel region.

### Claim 7 (depends on 6)

The method of claim 6, further comprising forming a doped punchthrough stop (PTS) layer beneath each the first semiconductor fin and the second semiconductor fin in response to doping the first semiconductor fin and the semiconductor fin.

### Claim 8

A method of forming a semiconductor device comprising:
patterning a semiconductor substrate including a first region and a second region so as to form a plurality of semiconductor fins;
recessing the first region with respect to a second region so as to form a first semiconductor fin in the first region having a first total height and a second semiconductor fin in the second region having a second total height that is less than the first total height;
reducing a thickness of a first portion of the first semiconductor fin so as to adjust a first resistance of the first semiconductor fin with respect to a second resistance of the second semiconductor fin; and
doping the first portion of the first semiconductor fin to form a finFET and entirely doping the second semiconductor fin to form a fin varactor.

### Claim 9 (depends on 8)

The method of claim 8, wherein recessing the first region further comprises:
depositing a masking layer atop the first and second regions so as to cover the first semiconductor fin and the second semiconductor fin, and selectively patterning the masking layer to expose the first region while maintaining coverage of the second region;
depositing a conformal spacer layer that covers sidewalls and an upper surface of the first semiconductor fin and an upper masking surface of the masking layer;
performing a first etching process selective to the conformal spacer layer so as to expose the semiconductor substrate of the first region; and
performing a second etching process selective to the semiconductor substrate so as to recess the first region with respect to the second region.

### Claim 10 (depends on 9)

The method of claim 9, wherein doping the first fin portion comprises:
forming spacers on sidewalls of the first semiconductor fin located between the upper surface and the first fin portion in response to the first etching process;
implanting dopants in the first fin portion; and
inhibiting doping implantation in a region of the first semiconductor fin covered by the spacers so as to form a self-aligned un-doped channel region.

### Claim 11 (depends on 10)

The method of claim 10, wherein reducing the thickness includes selectively etching the first region with respect to the spacers.

### Claim 12 (depends on 9)

The method of claim 9, further comprising forming a doped punchthrough stop (PTS) layer beneath each the first semiconductor fin and the second semiconductor fin in response to doping the first and second semiconductor fins.