# US 9,520,385 B1 · Package structure and method for forming same

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- Number: US 9,520,385 B1
- Document ID: US9520385B1
- Status: Granted
- Kind: B1
- Application number: 14/754,070
- Filed: 2015-06-29
- Published: 2016-12-29
- Granted: 2016-12-13
- Earliest claimed: 2015-06-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Hsien-Wei Chen; Kuo-Chuan Liu
- Web page: https://patentgrep.com/patent/US9520385B1

## CPC

- H10W 90/00: Package configurations
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/095: {of vias therein}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/635: {Through-vias}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 72/01: {Manufacture or treatment}
- H10W 72/073: {of die-attach connectors}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 72/874: {On different surfaces}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/9413: {on encapsulations}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A device comprises a bottom package comprising an interconnect structure, a molding compound layer over the interconnect structure, a semiconductor die in the molding compound layer and a solder layer embedded in the molding compound layer, wherein a top surface of the solder layer is lower than a top surface of the molding compound layer and a top package bonded on the bottom package through a joint structure formed by the solder layer and a bump of the top package.

## Claims

### Claim 1

A method comprising:
depositing a seed layer on a dielectric layer;
patterning a photoresist layer over the seed layer to form an opening;
forming a solder layer in the opening;
forming a conductive layer over the solder layer through a plating process;
attaching a semiconductor die on the dielectric layer;
forming a molding compound layer over the dielectric layer to form a bottom package, wherein the semiconductor die, the conductive layer and the solder layer are embedded in the molding compound layer;
applying a grinding process to the molding compound layer until a surface of the semiconductor die is exposed;
applying a dielectric removal process to the dielectric layer until a surface of the solder layer is exposed; and
mounting a top package on the bottom package.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
prior to the step of attaching the semiconductor die on the dielectric layer, removing the photoresist layer.

### Claim 3 (depends on 1)

The method of claim 1, wherein:
the top package comprises a bump and the bump of the top package and the solder layer form a joint structure during the step of mounting the top package on the bottom package, and wherein a lower portion of the joint structure is surrounded by the seed layer.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
prior to the step of forming the conductive layer over the solder layer through the plating process, depositing a nickel layer on the solder layer.

### Claim 5 (depends on 4)

The method of claim 4, wherein:
the nickel layer has a thickness in a range from about 0.5 μm to about 2 μm.

### Claim 6

A method comprising:
depositing a seed layer on a dielectric layer;
patterning a photoresist layer over the seed layer to form an opening;
forming a solder layer in the opening;
forming a nickel layer on and in contact with the solder layer;
plating a conductive material over the nickel layer;
removing remaining portions of the photoresist layer;
attaching a semiconductor die on the dielectric layer;
forming a molding compound layer over the dielectric layer to form a bottom package;
applying a grinding process to the molding compound layer until a surface of the semiconductor die is exposed;
removing a portion of the dielectric layer to expose a surface of the solder layer; and
mounting a top package on the bottom package.

### Claim 7 (depends on 6)

The method of claim 6, further comprising:
prior to the step of attaching the semiconductor die on the dielectric layer, etching exposed portions of the seed layer.

### Claim 8 (depends on 6)

The method of claim 6, wherein:
the semiconductor die is embedded in the molding compound layer after the step of forming the molding compound layer over the dielectric layer.

### Claim 9 (depends on 6)

The method of claim 6, further comprising:
forming an interconnect structure over the molding compound layer.

### Claim 10 (depends on 9)

The method of claim 9, wherein:
the interconnect structure comprises a metal line and a redistribution layer.

### Claim 11 (depends on 9)

The method of claim 9, wherein:
the interconnect structure is on and in contact with the molding compound layer; and
the interconnect structure is electrically coupled to the semiconductor die.

### Claim 12 (depends on 9)

The method of claim 9, further comprising:
forming a plurality of bumps over the interconnect structure, wherein the plurality of bumps are electrically connected to the semiconductor die through the interconnect structure.

### Claim 13 (depends on 6)

The method of claim 6, further comprising:
placing a bump of the top package against the nickel layer and the solder layer; and
applying a reflow process to the top package and the bottom package to form a joint structure.

### Claim 14 (depends on 6)

The method of claim 6, further comprising:
forming the nickel layer through a deposition process.

### Claim 15 (depends on 14)

The method of claim 14, wherein:
the nickel layer is of a thickness in a range from about 0.5 μm to about 2 μm.

### Claim 16

A method comprising:
depositing a seed layer on a dielectric layer;
patterning a photoresist layer over the seed layer to form a first opening and a second opening;
forming a first solder layer in the first opening and a second solder layer in the second opening;
plating a conductive material in the first opening and the second opening to form a first via and a second via;
attaching a semiconductor die on the dielectric layer;
forming a molding compound layer over the dielectric layer to form a bottom package, wherein the semiconductor die, the first via and the second via are embedded in the molding compound layer;
applying a grinding process to the molding compound layer until a surface of the semiconductor die is exposed;
removing portions of the dielectric layer to expose the first solder layer and the second solder layer; and
mounting a top package on the bottom package, wherein bumps of the top package, the first solder layer and the second solder layer form a joint structure.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
forming a first nickel layer on the first solder layer; and
forming a second nickel layer on the second solder layer.

### Claim 18 (depends on 17)

The method of claim 17, wherein:
the first nickel layer is between and in contact with the first solder layer and the first via; and
the second nickel layer is between and in contact with the second solder layer and the second via.

### Claim 19 (depends on 16)

The method of claim 16, further comprising:
prior to the step of attaching the semiconductor die on the dielectric layer, removing remaining portions of the photoresist layer.

### Claim 20 (depends on 16)

The method of claim 16, wherein:
the semiconductor die is between the first via and the second via.