# US 9,520,380 B2 · Wafer process for molded chip scale package (MCSP) with thick backside metallization

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- Number: US 9,520,380 B2
- Document ID: US9520380B2
- Status: Granted
- Kind: B2
- Application number: 14/950,997
- Filed: 2015-11-24
- Published: 2016-03-17
- Granted: 2016-12-13
- Earliest claimed: 2012-09-01
- Assignees: Alpha and Omega Semiconductor Incorporated
- Applicants: Alpha and Omega Semiconductor Incorporated
- Inventors: Yan Xun Xue; Hamza Yilmaz; Yueh-Se Ho; Jun Lu; Zhiqiang Niu; Guo Feng Lian
- Web page: https://patentgrep.com/patent/US9520380B2

## CPC

- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 50/00: Etching of wafers, substrates or parts of devices
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 70/20: Conductive package substrates serving as an interconnection, e.g. metal plates (leadframes H10W70/40)
- H10W 74/014: {using batch processing}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/01204: {using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates}
- H10W 72/0198: {batch processes}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate}
- H10W 72/232: {Plan-view shape, i.e. in top view}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/856: {Bump connectors and die-attach connectors (bumps embedded in underfills H10W74/15)}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A wafer process for molded chip scale package (MCSP) comprises: depositing metal bumps on bonding pads of chips on a wafer; forming a first packaging layer at a front surface of the wafer to cover the metal bumps; forming an un-covered ring at an edge of the wafer to expose two ends of each scribe line of a plurality of scribe lines; thinning the first packaging layer to expose metal bumps; forming cutting grooves; grinding a back surface of the wafer to form a recessed space and a support ring at the edge of the wafer; depositing a metal seed layer at a bottom surface of the wafer in the recessed space; cutting off an edge portion of the wafer; flipping and mounting the wafer on a substrate; depositing a metal layer covering the metal seed layer; removing the substrate from the wafer; and separating individual chips from the wafer by cutting through the first packaging layer, the wafer, the metal seed layers and the metal layers along the scribe lines.

## Claims

### Claim 1

A wafer process for molded chip scale package (MCSP) for packaging semiconductor chips formed at a front surface of a semiconductor wafer, each semiconductor chip comprising a plurality of metal bonding pads formed on a respective front surface of said each semiconductor chip, the wafer process comprising the steps of:
forming a respective metal bump on each of the plurality of metal bonding pads;
forming a first packaging layer at the front surface of the semiconductor wafer to cover the metal bumps, wherein a radius of the first packaging layer is smaller than a radius of the semiconductor wafer so as to form an un-covered ring at an edge of the semiconductor wafer, and wherein two ends of each scribe line of a plurality of scribe lines are located between two adjacent semiconductor chips and extend to a front surface of the un-covered ring;
thinning the first packaging layer to expose the metal bump from the first packaging layer;
forming a respective cutting groove on a front surface of the thinned first packaging layer along said each scribe line by cutting the first packaging layer along a straight line connecting the two ends of said each scribe line exposed on the front surface of the un-covered ring;
grinding at a back surface of the semiconductor wafer to form a recessed space at the back surface of the semiconductor wafer and a support ring at the edge of the semiconductor wafer;
depositing a metal seed layer at a bottom surface of the semiconductor wafer in the recessed space;
cutting off an edge portion of the semiconductor wafer;
flipping and mounting the semiconductor wafer on a substrate, the thinned first packaging layer being directly attached to a top surface of the substrate;
depositing a metal layer covering the metal seed layer;
removing the substrate from the semiconductor wafer; and
separating individual semiconductor chips from the semiconductor wafer by cutting through the first packaging layer, the semiconductor wafer, the metal seed layer and the metal layer along the cutting grooves, wherein the first packaging layer is cut into a plurality of top packaging layers, wherein a respective top packaging layer of the plurality of top packaging layers covers the front surface of said each semiconductor chip, wherein the respective metal bump is exposed from the respective top packaging layer of said each semiconductor chip, wherein the metal layer is cut into a plurality of bottom metal layers, and wherein a respective bottom metal layer of the plurality of bottom metal layers covers a back surface of said each semiconductor chip.

### Claim 2 (depends on 1)

The wafer process of claim 1, wherein the cutting groove extends to the front surface of the semiconductor wafer.

### Claim 3 (depends on 1)

The wafer process of claim 1, wherein cutting off the edge portion of the semiconductor wafer comprises cutting off the support ring.

### Claim 4 (depends on 3)

The wafer process of claim 3, wherein a radius of the recessed space is smaller than the radius of the first packaging layer so that a portion of the first packaging layer is overlapped with a portion of the support ring, and wherein cutting off the edge portion of the semiconductor wafer comprises cutting off the support ring and the overlapped portion of the first packaging layer.

### Claim 5 (depends on 1)

The wafer process of claim 1, before depositing the metal seed layer, further comprising depositing another metal layer at the bottom surface of the semiconductor wafer in the recessed space for an Ohmic contact so as to form a barrier for the metal seed layer not to diffuse into the semiconductor wafer.

### Claim 6 (depends on 1)

The wafer process of claim 1, wherein the recessed space is formed by a grinding wheel with a radius smaller than the radius of the semiconductor wafer.

### Claim 7 (depends on 1)

The wafer process of claim 1, after depositing the metal layer covering the metal seed layer, further comprising forming a second packaging layer on the metal layer, wherein separating the individual semiconductor chips from the semiconductor wafer comprises cutting through the first packaging layer, the semiconductor wafer, the seed layer, the metal layer and the second packaging layer along the cutting grooves, wherein the second packaging layer is cut into a plurality of bottom packaging layers, and wherein a respective bottom packaging layer of the plurality of bottom packaging layers covers the respective bottom metal layer of said each semiconductor chip.

### Claim 8 (depends on 1)

The wafer process of claim 1, wherein the seed layer is deposited by evaporation or sputtering.

### Claim 9 (depends on 8)

The wafer process of claim 8, wherein a material of the seed layer is selected from the group consisting of TiNiAg, TiNi, and TiNiAl.

### Claim 10 (depends on 8)

The wafer process of claim 8, wherein the metal layer is deposited by electroplating and/or electroless plating.

### Claim 11 (depends on 10)

The wafer process of claim 10, wherein a material of the metal layer is selected from the group consisting of Ag, Cu, and Ni.

### Claim 12 (depends on 1)

The wafer process of claim 1, wherein the thinned first packaging layer is thicker than the semiconductor wafer after the step of grinding at the back surface of the semiconductor wafer.

### Claim 13

A wafer process for molded chip scale package (MCSP) for packaging semiconductor chips formed at a front surface of a semiconductor wafer, each semiconductor chip comprising a plurality of metal bonding pads formed on a respective front surface of said each semiconductor chip, the wafer process comprising the steps of:
forming a respective metal bump on each of the plurality of metal bonding pads;
forming a first packaging layer at the front surface of the semiconductor wafer to cover the metal bumps, wherein a radius of the first packaging layer is smaller than a radius of the semiconductor wafer so as to form an un-covered ring at an edge of the semiconductor wafer, and wherein two ends of each scribe line of a plurality of scribe lines are located between two adjacent semiconductor chips and extend to a front surface of the un-covered ring;
thinning the first packaging layer to expose the metal bump from the first packaging layer;
forming a respective cutting groove on a front surface of the thinned first packaging layer along said each scribe line by cutting the first packaging layer along a straight line connecting the two ends of said each scribe line exposed on the front surface of the un-covered ring;
grinding at a back surface of the semiconductor wafer to form a recessed space at the back surface of the semiconductor wafer and a support ring at the edge of the semiconductor wafer;
depositing a metal seed layer at a bottom surface of the semiconductor wafer in the recessed space;
cutting off an edge portion of the semiconductor wafer;
flipping and mounting the semiconductor wafer on a substrate, the thinned first packaging layer being directly attached to a top surface of the substrate;
depositing a metal layer covering the metal seed layer;
removing the substrate from the semiconductor wafer; and
separating individual semiconductor chips from the semiconductor wafer by cutting through the first packaging layer, the semiconductor wafer, the metal seed layer and the metal layer along the cutting grooves, wherein the first packaging layer is cut into a plurality of top packaging layers, wherein a respective top packaging layer of the plurality of top packaging layers covers the front surface of said each semiconductor chip, wherein the respective metal bump is exposed from the respective top packaging layer of said each semiconductor chip, wherein the metal layer is cut into a plurality of bottom metal layers, and wherein a respective bottom metal layer of the plurality of bottom metal layers covers a back surface of said each semiconductor chip;
wherein the metal layer is more than one tenth of a thickness of the semiconductor wafer after the step of depositing the metal layer covering the metal seed layer.